Three-dimensional memory array incorporating serial chain diode stack
First Claim
1. A multi-level memory array comprising:
- on alternate levels of the memory array, a respective plurality of parallel spaced-apart rail-stacks disposed above the substrate running in a first direction;
on the other levels of the memory array, a respective plurality of parallel spaced-apart rail-stacks disposed above the substrate and running in a second direction different than the first direction, such that a projection of the rail-stacks on one level to the rail-stacks on an adjacent level defines intersections therebetween; and
a layer of low conducting material separating the rail-stacks on one level from the rail-stacks on an adjacent level, the layer of low conducting material at each intersection of rail-stacks separating a first conductivity type doped semiconductor material in the rail-stack below the intersection from a material other than a first conductivity type doped semiconductor material in the rail-stack above the intersection.
5 Assignments
0 Petitions
Accused Products
Abstract
A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.
-
Citations
41 Claims
-
1. A multi-level memory array comprising:
-
on alternate levels of the memory array, a respective plurality of parallel spaced-apart rail-stacks disposed above the substrate running in a first direction;
on the other levels of the memory array, a respective plurality of parallel spaced-apart rail-stacks disposed above the substrate and running in a second direction different than the first direction, such that a projection of the rail-stacks on one level to the rail-stacks on an adjacent level defines intersections therebetween; and
a layer of low conducting material separating the rail-stacks on one level from the rail-stacks on an adjacent level, the layer of low conducting material at each intersection of rail-stacks separating a first conductivity type doped semiconductor material in the rail-stack below the intersection from a material other than a first conductivity type doped semiconductor material in the rail-stack above the intersection. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
the layer of low conducting material at each intersection of rail-stacks separates a first conductivity type doped semiconductor material in the rail-stack below the intersection from a metallic layer in the rail-stack above the intersection.
-
-
3. The memory array defined by claim 1 wherein:
the layer of low conducting material at each intersection of rail-stacks separates a first conductivity type doped semiconductor material in the rail-stack below the intersection from a second conductivity type doped semiconductor material in the rail-stack above the intersection.
-
4. The memory array defined by claim 3 wherein the semiconductor material is silicon, and the silicon on one side of each said intersection is more lightly doped than the silicon on the opposite side of said respective intersection.
-
5. The memory array defined by claim 4 wherein the side of the intersection having the more lightly doped silicon includes a more heavily doped silicon region disposed between the more lightly doped silicon and its respective conductor.
-
6. The memory array defined by claim 5 wherein the low conducting material comprises silicon dioxide.
-
7. The memory array defined by claim 5 wherein the low conducting material layer comprises silicon nitride.
-
8. The memory array defined by claim 5 wherein the low conducting material layer comprises undoped silicon.
-
9. The memory array defined by claim 5 wherein the rail-stacks include a conductor comprising a metal.
-
10. The memory array defined by claim 9 wherein each rail-stack conductor is sandwiched between silicon layers.
-
11. The memory array defined by claim 1 wherein:
the layer of low conducting material at each intersection of rail-stacks can be changed to a higher conducting state to program the array.
-
12. The memory array defined by claim 1 wherein the semiconductor material is silicon.
-
13. The memory array defined by claim 12 wherein the passage of a sufficient current from one of the rail-stacks on a level to one of the rail-stacks on an adjacent level causes a diode to form at the intersection of these respective rail-stacks.
-
14. The memory array defined by claim 13 wherein the diode formed at each intersection of rail-stacks is a p+n−
- doped silicon diode.
-
15. The memory array defined by claim 14 wherein the layer of low conducting material at each level is silicon dioxide.
-
16. The memory array defined by claim 15 wherein the layer of low conducting material is substantially continuous at each level.
-
17. The memory array defined by claim 16 wherein the layer of low conducting material is blanket deposited.
-
18. The memory array defined by claim 16 wherein the dielectric layer comprises ONO.
-
19. The memory array defined by claim 13 wherein the diode formed at each intersection of rail-stacks is a p−
- n+ doped silicon diode.
-
20. The memory array defined by claim 13 wherein the diode formed at each intersection of rail-stacks is a Schottky diode.
-
21. The memory array defined by claim 1 wherein the layer of low conducting material provides a physical barrier between vertically adjacent rail-stacks, substantially minimizing sidewall leakage.
-
22. The memory array defined by claim 1 wherein each rail-stack comprises:
-
a conductor sandwiched between respective silicon layers above and below the conductor; and
the silicon layer above the conductor is of a first conductivity type for all rail-stacks.
-
-
23. The memory array defined by claim 1 wherein the layer of low conducting material is grown from a semiconductor layer.
-
24. A multi-level memory array comprising:
-
on alternate levels of the memory array, a respective plurality of parallel spaced-apart conductors disposed above the substrate running in a first direction;
on the other levels of the memory array, a respective plurality of parallel spaced-apart conductors disposed above the substrate and running in a second direction different than the first direction, such that a projection of the conductors on one level to the conductors on an adjacent level defines intersections therebetween; and
a programmable layer of material separating the conductors on one level from the conductors on an adjacent level, the programmable layer of material at each intersection of conductors having a conductivity capable of being modified by application of a voltage and forming, at least before or after the application of the voltage, a steering device between successive levels of conductors;
wherein the steering devices between successive levels of conductors are each oriented in a like direction. - View Dependent Claims (25, 26, 27, 28, 29)
-
-
30. A multi-level non-volatile memory array comprising:
-
a plurality of first conductors disposed at a first and third level running generally in a first direction above a substrate;
a plurality of second conductors disposed at a second and fourth level above the substrate and running in a second direction, and a plurality of dielectric regions each disposed respectively between successive levels of the first and second conductors which are capable of being selectively breached to form a diode between successive levels of the first and second conductors;
wherein the resulting diodes between successive levels of the first and second conductors are each oriented in a like direction. - View Dependent Claims (31, 32)
each of the plurality of first conductors are sandwiched between layers of silicon; and
each of the plurality of second conductors are sandwiched between layers of silicon.
-
-
32. The array defined by claim 31 wherein:
the first and second conductors are sandwiched between layers of silicon of opposite conductivity type doping.
-
33. A multi-level non-volatile memory array comprising:
-
a plurality of first rail-stacks disposed at a first and third level running generally in a first direction above a substrate;
a plurality of second rail-stacks disposed at a second and fourth level above the substrate and running in a second direction, and a plurality of dielectric regions each disposed respectively between successive levels of the first and second rail-stacks which are capable of being selectively breached to form a diode between successive levels of the first and second rail-stacks;
wherein the resulting diodes between successive levels of the first and second rail-stacks are each oriented in a like direction. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
each of the plurality of first rail-stacks comprises first conductors sandwiched between layers of silicon; and
each of the plurality of second rail-stacks comprises second conductors sandwiched between layers of silicon.
-
-
35. The array defined by claim 34 wherein:
the first and second conductors are sandwiched between layers of silicon of opposite conductivity type doping.
-
36. The array defined by claim 34 wherein:
-
the layers of silicon on at least one side of the first conductors are more heavily doped adjacent to the first conductor than they are further from the first conductor; and
the layers of silicon on at least one side of the second conductors are more heavily doped adjacent to the second conductors than they are further from the second conductors.
-
-
37. The array defined by claim 36 wherein the resulting diodes formed are p+n−
- diodes.
-
38. The array defined by claim 36 wherein the resulting diodes formed are p−
- n+ diodes.
-
39. The array defined by claim 33 wherein the dielectric regions are blanket deposited dielectric layers.
-
40. The array defined by claim 38 where the dielectric layers are substantially continuous, forming a physical barrier between levels of rail-stacks.
-
41. The array defined by claim 33 wherein the dielectric regions are grown from one of the layers of silicon.
Specification