Non-volatile semiconductor memory device and data programming method

• US 6,785,166 B2
• Filed: 04/16/2003
• Issued: 08/31/2004
• Est. Priority Date: 08/27/1993
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iwahashi, Hiroshi
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US10/414,344
• Publication Number:
  US 20030210571A1
• Time in Patent Office: 503 Days
• Field of Search: 365/185.24, 365/185.17, 365/185.19, 365/185.22, 365/185.28, 365/185.29, 365/189.05
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

Claims

1. A non-volatile semiconductor memory device, comprising:

a memory cell array including electrically erasable and programmable read only memory cells arranged in a matrix form having row lines and column lines, each of the memory cells including an N channel type MOS transistor having an N type drain region, an N type source region, a floating gate formed above an entire channel region located between the N type drain region and the N type source region, and a control gate, and each of the memory cells storing data in accordance with a charged state of the floating gate, the charged state of the floating gate being at least a first charged state or a second charged state, a threshold voltage of the memory cell in the first charged state being a positive value that is lower than a threshold voltage of the memory cell in the second charged state, the control gates of the memory cells in a same row being commonly connected to one of the row lines, the drain regions of the memory cells in a same column being commonly connected to one of the column lines, and the memory cell array being formed in a P type well region;

column gate transistors, each connected to corresponding each of the column lines, each for selecting the column line, the gates of the column gate transistors being connected to a column decoder, the column gate transistors being of an N channel type, and being not formed in the P type well region, but in a semiconductor substrate;

erasing means, connected to the P type well region, for making the floating gate discharge electrons to the P type well region in order to erase the memory cell, the memory cell being erased when an erasing voltage is applied to the P type well region by the erasing means, the erasing operation being simultaneously performed on the memory cells connected to the row lines and the column lines, and electrons being discharged from the floating gate of the memory cell to the P type well region by the electron tunnel effect;

programming means for programming the memory cells, the programming means injecting electrons to the floating gate of the memory cell by applying a high gate voltage and a high drain voltage to the row line and the column line to selectively program the memory cell with desired data, electrons being injected to the floating gate of the memory cell by allowing a channel current to flow from the drain to the source of the memory cell;

voltage generating means for generating the erasing voltage, the high gate voltage and the high drain voltage, in order to inject electrons to the floating gate, and to make the floating gate discharge electrons, the erasing voltage being generated by the use of a voltage which is generated from a power source voltage externally applied, the high gate voltage being generated by the use of a voltage which is generated from the power source voltage externally applied, and the high drain voltage being generated by the use of a voltage which is generated from the power source voltage externally applied; and

current path breaking means for breaking a discharging current path from the column line via the memory cells, electrons in the floating gates of the memory cells being discharged by the erasing means, and the memory cells being connected to a row line that is not the row line connected to the selected memory cell, when electrons are injected to the floating gate of the selected memory cell by setting the high gate voltage to be at a first predetermined voltage by the programming means after the floating gate of the memory cell is made to discharge electrons by the erasing means, or when data is read out from the selected memory cell,

wherein the memory cell is set to be in the first charged state by setting the high gate voltage to be at the first predetermined voltage by the programming means after the erasing means make the floating gate of the memory cell discharged electrons in order to inject electrons to the floating gate of the memory cell, and thereafter, the memory cell is set to be in the second charged state by setting the high gate voltage to be at a second predetermined voltage, which is higher than the first predetermined voltage, by the programming means, and selectively injecting electrons to the floating gate of the memory cell, thereby programming data are programmed into the memory cells.

2. The non-volatile semiconductor memory device as defined in claim 1, wherein:

the current path breaking means includes a decoding transistor;

the source of the memory cell is connected to a ground potential via the decoding transistor;

the decoding transistor is controlled by a decoding signal;

the source of the memory cell connected to the selected row line is connected to the ground potential via the decoding transistor in order to apply the ground potential to the source of the selected memory cell; and

the decoding transistors connected to the sources of the memory cells connected to non-selected row lines are turned off in order to break current paths connecting to the column line via the memory cells connected to the non-selected row lines, when electrons are injected to the floating gate of the selected memory cell by setting the high gate voltage to be at the first predetermined voltage by the programming means after the floating gate of the memory cell is made to discharge electrons by the erasing means, or when data is read out from the selected memory cell.

3. The non-volatile semiconductor memory device as defined in claim 1, wherein:

when the memory cells are erased;

the row lines are at a ground potential; and

electrons are discharged from the floating gates of the memory cells to the P type well region by applying the erasing voltage having a high positive voltage value to the P type well region by the erasing means.

4. The non-volatile semiconductor memory device as defined in claim 2, wherein:

when the memory cells are erased;

the row lines are at a ground potential; and

electrons are discharged from the floating gates of the memory cells to the P type well region by applying the erasing voltage having a high positive voltage value to the P type well region by the erasing means.

5. A non-volatile semiconductor memory device, comprising:

a memory cell array including electrically erasable and programmable read only memory cells arranged in a matrix form having row lines and column lines, each of the memory cells including an N channel type MOS transistor having an N type drain region, an N type source region, a floating gate formed above an entire channel region located between the N type drain region and the N type source region, and a control gate, and each of the memory cells storing data in accordance with a charged state of the floating gate, the charged state of the floating gate being at least a first charged state or a second charged state, a threshold voltage of the memory cell in the first charged state being a positive value that is lower than a threshold voltage of the memory cell in the second charged state, the control gates of the memory cells in a same row being commonly connected to one of the row lines, the drain regions of the memory cells in a same column being commonly connected to one of the column lines, and the memory cell array being formed in a P type well region;

erasing means, connected to the P type well region, for making the floating gate discharge electrons to the P type well region in order to erase the memory cell, the memory cell being erased when an erasing voltage is applied to the P type well region by the erasing means, the erasing operation being simultaneously performed on the memory cells connected to the row lines and the column lines, and electrons being discharged from the floating gate of the memory cell to the P type well region by the electron tunnel effect;

programming means for programming the memory cells, the programming means injecting electrons to the floating gate of the memory cell by applying a high gate voltage and a high drain voltage to the row line and the column line to selectively program the memory cell with desired data, electrons being injected to the floating gate of the memory cell by allowing a channel current to flow from the drain to the source of the memory cell;

voltage generating means for generating the erasing voltage, the high gate voltage and the high drain voltage, in order to inject electrons to the floating gate, and to make the floating gate discharge electrons, the erasing voltage being generated by the use of a voltage which is generated from a power source voltage externally applied, the high gate voltage being generated by the use of a voltage which is generated from the power source voltage externally applied, and the high drain voltage being generated by the use of a voltage which is generated from the power source voltage externally applied; and

current path breaking means for breaking a discharging current path from the column line via the memory cells, electrons in the floating gates of the memory cells being discharged by the erasing means, and the memory cells being connected to a row line that is not the row line connected to the selected memory cell, when electrons are injected to the floating gate of the selected memory cell by setting the high gate voltage to be at a first predetermined voltage by the programming means after the floating gate of the memory cell is made to discharge electrons by the erasing means, or when data is read out from the selected memory cell,

wherein the memory cell is set to be in the first charged state by setting the high gate voltage to be at the first predetermined voltage by the programming means after the erasing means make the floating gate of the memory cell discharged electrons in order to inject electrons to the floating gate of the memory cell, and thereafter, the memory cell is set to be in the second charged state by setting the high gate voltage to be at a second predetermined voltage, which is higher than the first predetermined voltage, by the programming means, and selectively injecting electrons to the floating gate of the memory cell, thereby programming data are programmed into the memory cells.

6. The non-volatile semiconductor memory device as defined in claim 5, wherein:

the current path breaking means includes a decoding transistor;

the source of the memory cell is connected to a ground potential via the decoding transistor;

the decoding transistor is controlled by a decoding signal;

the source of the memory cell connected to the selected row line is connected to the ground potential via the decoding transistor in order to apply the ground potential to the source of the selected memory cell; and

the decoding transistors connected to the sources of the memory cells connected to non-selected row lines are turned off in order to break current paths connecting to the column line via the memory cells connected to the non-selected row lines, when electrons are injected to the floating gate of the selected memory cell by setting the high gate voltage to be at the first predetermined voltage by the programming means after the floating gate of the memory cell is made to discharge electrons by the erasing means, or when data is read out from the selected memory cell.

7. The non-volatile semiconductor memory device as defined in claim 5, wherein:

when the memory cells are erased;

the row lines are at a ground potential; and

electrons are discharged from the floating gates of the memory cells to the P type well region by applying the erasing voltage having a high positive voltage value to the P type well region by the erasing means.

8. The non-volatile semiconductor memory device as defined in claim 6, wherein:

when the memory cells are erased;

the row lines are at a ground potential; and

electrons are discharged from the floating gates of the memory cells to the P type well region by applying the erasing voltage having a high positive voltage value to the P type well region by the erasing means.