Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer

• US 6,790,733 B1
• Filed: 03/28/2003
• Issued: 09/14/2004
• Est. Priority Date: 03/28/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Mo, Renee T., Deshpande, Sadanand V., OʼNeil, Patricia A., Doris, Bruce B., Natzle, Wesley C.
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US10/249,296
• Publication Number:
  US 20040191998A1
• Time in Patent Office: 536 Days
• Field of Search: 438/197, 438/199, 438/230, 438/299, 438/300, 438/303, 438/585, 438/595, 438/976
• US Class Current: 438/300
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 438/976 Temporary protective layer

Abstract

The present invention provides a method for preserving an oxide hard mask for the purpose of avoiding growth of epi Si on the gate stack during raised source/drain formation. The oxide hard mask is preserved in the present invention by utilizing a method which includes a chemical oxide removal processing step instead of an aqueous HF etchant.

Claims

1. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising the steps of:

(a) providing a material stack atop a surface of a semiconductor substrate, said material stack comprising an oxide hard mask located atop a gate conductor, which is located atop a gate dielectric;

(b) patterning said oxide hard mask and said gate conductor of said material stack;

(c) performing a post etch cleaning step utilizing a first chemical oxide removal (COR) step;

(d) forming a disposable spacer on at least each sidewall of said patterned gate conductor;

(e) removing portions of said gate dielectric not protected by said disposable spacers and said patterned gate conductor to expose portions of said semiconductor substrate wherein said removing comprises a second chemical oxide removal step;

(f) forming raised source/drain regions in said exposed portions of the semiconductor substrate; and

(g) removing said disposable spacers to expose portions of said semiconductor substrate abutting the patterned gate coductor.

2. The method of claim 1 further comprising the steps of:

forming source/drain extension regions in portions of said semiconductor substrate that are left exposed after removing step g; and

forming source/drain regions in at least said raised source/drain regions.

3. The method of claim 1 wherein said oxide hard mask is comprised of an oxide formed by chemical vapor deposition of tetraethylorthosilicate.

4. The method of claim 1 wherein said first COR process comprises a gaseous mixture of HF and ammonia.

5. The method of claim 4 wherein said gaseous mixture of HF and ammonia comprises a ratio of 2 parts HF and 1 part ammonia.

6. The method of claim 1 wherein said first COR process is performed at a pressure between 1 mTorr and at a temperature of about 25°

C.

7. The method of claim 1 wherein said disposable spacers are comprised of SiO₂.

8. The method of claim 1 wherein said second COR process comprises a gaseous mixture of HF and ammonia.

9. The method of claim 8 wherein said gaseous mixture of HF and ammonia comprises a ratio of 2 parts HF and 1 part ammonia.

10. The method of claim 1 wherein said second COR process is performed at a pressure between 1 mTorr and at a temperature of about 25°

C.

11. The method of claim 10 wherein said second COR process results in the formation of a solid reaction product.

12. The method of claim 11 wherein said solid reaction product is removed by heating to a temperature of about 100°

C., rinsing in water, or an aqueous solution.

13. The method of claim 11 wherein said solid reaction product is removed by heating to a temperature of about 100°

C. and with an aqueous HF solution.

14. The method of claim 1 wherein step (f) comprises an epi Si growth process.

15. The method of claim 1 further comprising forming source/drain regions prior to the removing of the disposable spacers.

16. The method of claim 1 wherein said removing of the disposable spacers further comprises the removing of the oxide hard mask and the removing of the gate dielectric underlying the disposable spacers.

17. The method of claim 1 wherein said removing of the disposable spacers does not remove the oxide hard mask and the underlying gate dielectric.

18. The method of claim 17 wherein the disposable spacers are removed by hot phosphoric acid.

19. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising the steps of:

(a) providing a material stack atop a surface of a semiconductor substrate, said material stack comprising an oxide hard mask located atop a gate conductor, which is located atop a gate dielectric;

(b) patterning said oxide hard mask and said gate conductor of said material stack;

(c) performing a post etch cleaning step utilizing a first chemical oxide removal (COR) step;

(d) forming a disposable spacer comprising SiO₂ on at least each sidewall of said patterned gate conductor;

(e) removing portions of said gate dielectric not protected by said disposable spacers and said patterned gate conductor to expose portion of said semiconductor, wherein said removing comprising a second COR step;

(f) forming raised source/drain regions in said exposed portions of the semiconductor substrate; and

(g) removing said disposable spacers to expose portions of said semiconductor substrate abutting the patterned gate conductor.

20. The method of claim 19 wherein said first and second COR steps comprise a gaseous mixture of HF and ammonia.

21. The method of claim 19 wherein said removing of the disposable spacers further comprises the removing of the oxide hard mask and the removing of the gate dielectric underlying the disposable spacers.

22. The method of claim 19 wherein said removing of the disposable spacers does not remove the oxide hard mask and the underlying gate dielectric.

23. The method of claim 19 wherein the disposable spacers are removed by hot phosphoric acid.