Bidirectional port with clock channel used for synchronization
First Claim
1. A bi-directional port circuit comprising:
- a data transceiver;
a clock driver with an enable input node;
a control circuit to drive the enable input node when the data transceiver is initialized; and
a clock receiver circuit having a clock detection circuit to detect the presence of an incoming clock signal;
wherein the control circuit comprises an initialization circuit to initialize the data transceiver.
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Accused Products
Abstract
A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.
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Citations
27 Claims
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1. A bi-directional port circuit comprising:
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a data transceiver;
a clock driver with an enable input node;
a control circuit to drive the enable input node when the data transceiver is initialized; and
a clock receiver circuit having a clock detection circuit to detect the presence of an incoming clock signal;
wherein the control circuit comprises an initialization circuit to initialize the data transceiver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
a voltage mode output driver having an output node; and
a data receiver having an input node coupled to the output node of the voltage mode driver.
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3. The bi-directional port circuit of claim 1 wherein the data transceiver comprises:
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a current mode output driver having a differential output node; and
a data receiver having a differential input node coupled to the differential output node of the current mode driver.
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4. The bi-directional port circuit of claim 1 wherein the initialization circuit comprises an impedance control circuit.
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5. The bi-directional port circuit of claim 4 wherein the control circuit is operative to enable the clock driver when the impedance control circuit has initialized an impedance of the data transceiver.
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6. The bi-directional port circuit of claim 5 wherein:
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the data transceiver includes a voltage mode driver having an output impedance; and
the impedance initialized by the impedance control circuit is the output impedance of the voltage mode driver.
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7. The bi-directional port circuit of claim 5 wherein:
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the data transceiver includes a current mode driver having at least one termination resistor; and
the impedance initialized by the impedance control circuit is the at least one termination resistor.
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8. The bi-directional port circuit of claim 1 wherein:
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the data transceiver includes a variable current source circuit; and
the initialization circuit is operative to initialize the variable current source circuit.
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9. The bi-directional port circuit of claim 1 wherein:
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the data transceiver includes a receiver circuit having a variable offset; and
the initialization circuit is operable to initialize the variable offset of the receiver circuit.
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10. An integrated circuit comprising:
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an output driver to drive a data signal on a data node external to the integrated circuit;
an initialization circuit to initialize the output driver; and
a clock driver responsive to the initialization circuit such that the clock driver drives an outbound clock signal off the integrated circuit when the output driver is initialized;
wherein the output driver is a voltage mode driver with a programmable output impedance. - View Dependent Claims (11, 12, 13, 14)
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15. An integrated circuit comprising:
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an output driver to drive a data signal on a data node external to the integrated circuit;
an initialization circuit to initialize the output driver; and
a clock driver responsive to the initialization circuit such that the clock driver drives an outbound clock signal off the integrated circuit when the output driver is initialized;
wherein the output driver is a current mode driver with a variable current source; and
wherein the initialization circuit is operative to initialize the variable current source.
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16. An integrated circuit comprising:
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an output driver to drive a data signal on a data node external to the integrated circuit;
an initialization circuit to initialize the output driver; and
a clock driver responsive to the initialization circuit such that the clock driver drives an outbound clock signal off the integrated circuit when the output driver is initialized;
wherein the output driver is a current mode driver with a variable termination resistor; and
wherein the initialization circuit is operative to initialize the variable termination resistor. - View Dependent Claims (17, 18, 19, 20)
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21. An integrated circuit comprising:
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an output driver to drive a data signal on a data node external to the integrated circuit;
an initialization circuit to initialize the output driver; and
a clock driver responsive to the initialization circuit such that the clock driver drives an outbound clock signal off the integrated circuit when the output driver is initialized;
wherein the integrated circuit is a circuit type from the group consisting of;
a processor, a processor peripheral, a memory, and a memory controller.
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22. An electronic system comprising:
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a first integrated circuit having a first simultaneous bi-directional port comprising a first data driver, a first data receiver, a first clock driver with a first enable input node, and a first clock receiver with a first clock detect circuit; and
a second integrated circuit having a second simultaneous bi-directional port comprising a second data driver, a second data receiver, a second clock driver with a second enable input node, and a second clock receiver with a second clock detect circuit;
wherein output nodes of the first and second data drivers are coupled in common with input nodes of the first and second data receivers, the first and second integrated circuits include initialization circuits, and the first and second enable input nodes are coupled to the initialization circuits to enable clock signals after the first and second simultaneous bi-directional ports are initialized. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification