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CPU power sequence for large multiprocessor systems

  • US 6,792,553 B2
  • Filed: 12/29/2000
  • Issued: 09/14/2004
  • Est. Priority Date: 12/29/2000
  • Status: Expired due to Term
First Claim
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1. A computer system, comprising:

  • a power supply coupled to a control logic, said power supply including a first control signal and Power output lines, wherein said first control signal notifies the control logic when the Power output lines have stabilized;

    a plurality of voltage regulator modules (“

    VRM”

    ) coupled to said control logic, wherein each VRM receives a second control signal from the control logic indicating that the Power lines have stabilized; and

    a plurality of processors, each of said processors coupled to an individual VRM, wherein said VRMs sequentially transmit voltage to power-on the plurality of processors so that at least two of the plurality of processors do not start to power-on simultaneously.

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