CPU power sequence for large multiprocessor systems
First Claim
1. A computer system, comprising:
- a power supply coupled to a control logic, said power supply including a first control signal and Power output lines, wherein said first control signal notifies the control logic when the Power output lines have stabilized;
a plurality of voltage regulator modules (“
VRM”
) coupled to said control logic, wherein each VRM receives a second control signal from the control logic indicating that the Power lines have stabilized; and
a plurality of processors, each of said processors coupled to an individual VRM, wherein said VRMs sequentially transmit voltage to power-on the plurality of processors so that at least two of the plurality of processors do not start to power-on simultaneously.
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Accused Products
Abstract
A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the Power output lines have stabilized. The computer system also includes a plurality of voltage regulator modules (“VRM”) coupled to the control logic, wherein each VRM receives a power good signal from the control logic. A plurality of processors is also present in the computer system, each of the processors coupled to a VRM. Each of the VRMs transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good (“VRMP_G”) signal. The control logic includes means to control the sequential power-on of the processors so as to reduce the current sourcing requirements of the power supply and eliminate power supply surges.
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Citations
29 Claims
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1. A computer system, comprising:
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a power supply coupled to a control logic, said power supply including a first control signal and Power output lines, wherein said first control signal notifies the control logic when the Power output lines have stabilized;
a plurality of voltage regulator modules (“
VRM”
) coupled to said control logic, wherein each VRM receives a second control signal from the control logic indicating that the Power lines have stabilized; and
a plurality of processors, each of said processors coupled to an individual VRM, wherein said VRMs sequentially transmit voltage to power-on the plurality of processors so that at least two of the plurality of processors do not start to power-on simultaneously. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of powering on processors in a computer system that reduces the current source requirements of the computer system'"'"'s power supply, comprising:
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a) asserting a first control signal from the power supply after output lines of the power supply have stabilized;
b) placing all processors of the computer system into a reset state; and
c) driving a second control signal to a first voltage regulator module (“
VRM”
).d) waiting a first programmable delay for the VRM to stabilize its voltage output lines to appropriate levels; and
e) driving a third control signal to the processor coupled to the VRM and to the control logic after the VRM voltage output lines have stabilized;
f) waiting a second programmable delay for the processor coupled to the VRM to reach a stable electrical state;
g) determining whether all processors in the computer system are powered on;
h) driving another second control signal to the next VRM and repeating d) through g) if all processors in the computer system are not powered on; and
i) taking all processors out of reset and beginning hardware initialization if all processors are powered on after waiting a third programmable delay.
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10. A computer system, comprising:
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an intelligent power supply including a control logic, said power supply including a plurality of first control signals and Power output lines;
a plurality of voltage regulator modules (“
VRM”
) coupled to said intelligent power supply, wherein each VRM receives a first control signal from the intelligent power supply, after the control logic receives an indication from the power supply that the power output lines have become stable; and
a plurality of processors, each of said processors coupled to an individual VRM, wherein said VRMs sequentially transmits voltage to power-on the plurality of processors so that at least two of the plurality of processors do not start to power-on simultaneously. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A computer system, comprising:
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a power supply coupled to a control module, said power supply including a first control signal and Power output lines, wherein said first control signal notifies the control module when the Power output lines have stabilized;
a plurality of voltage regulator modules (“
VRM”
) coupled to said control module, wherein each VRM receives a second control signal from the control module indicating that the Power lines have stabilized; and
a plurality of computer servers organized in racks in a cabinet, each of said computer servers coupled to an individual VRM, wherein said VRMs sequentially transmit voltage to power-on the plurality computer servers so that at least two of the plurality of computer servers do not start to power-on simultaneously. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. A system, comprising:
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a power supply, wherein the power supply includes a first control signal and a set of power output lines;
control logic coupled to the power supply, wherein the control logic receives the first control signal and includes a set of second control signals;
a plurality of voltage regulator modules (VRMs) coupled to the control logic, wherein each VRM receives at least one of the set of second control signals and at least one of the power output lines;
a plurality of processors coupled to the plurality of VRMs, wherein each processor is coupled to an individual VRM by a third control signal;
wherein the control logic is configured to wait a first programmable delay before asserting each of the set of second control signals, and the individual VRM asserts the third control signal after a second programmable delay. - View Dependent Claims (28, 29)
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Specification