Charge pump circuit, passive buffer that employs the charge pump circuit, and pass gate that employs the charge pump circuit
First Claim
1. A buffer comprising:
- a) an input node;
b) an output node;
a first transistor comprising a first transistor first node connected to said input node, a first transistor second node connected to said output node, and a first transistor control node;
a second transistor comprising a second transistor first node connected to a first predetermined voltage node, a second transistor second node connected to said first transistor control node, and a second transistor control node connected to said first predetermined voltage node;
a capacitive element connected between said second transistor first node and said output node; and
a third transistor comprising a third transistor first node connected to said second transistor, second node, a third transistor second node connected to a second predetermined voltage node, and a third transistor control node connected to a third preselected voltage node.
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Accused Products
Abstract
Buffer that includes an input node, an output node, and a three-transistor charge pump circuit is coupled to the input node and the output node. The buffer generates an output signal that is a delayed version of a signal presented at the input node. The three-transistor charge pump includes a first transistor (e.g., a pass transistor) that includes a drain electrode that is coupled to the input node, a gate electrode and a source electrode; a second transistor that includes a drain electrode that is coupled to a first predetermined voltage, a gate electrode coupled to the drain electrode of the second transistor, and a source electrode coupled to the gate electrode of the first transistor; and a capacitive element that includes a first electrode that is coupled to the source electrode of the second transistor and the gate electrode of the first transistor and a second electrode that is coupled to the output node.
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Citations
9 Claims
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1. A buffer comprising:
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a) an input node;
b) an output node;
a first transistor comprising a first transistor first node connected to said input node, a first transistor second node connected to said output node, and a first transistor control node;
a second transistor comprising a second transistor first node connected to a first predetermined voltage node, a second transistor second node connected to said first transistor control node, and a second transistor control node connected to said first predetermined voltage node;
a capacitive element connected between said second transistor first node and said output node; and
a third transistor comprising a third transistor first node connected to said second transistor, second node, a third transistor second node connected to a second predetermined voltage node, and a third transistor control node connected to a third preselected voltage node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
said first transistor first node is a drain, said first transistor second node is a source, and said first transistor control node is a gate;
said second transistor first node is a drain, said second transistor second node is a source, and said second transistor control node is a gate; and
said third transistor first node is a drain, said third transistor second node is a source, and said third transistor control node is a gate.
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8. The buffer of claim 1, wherein;
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said first transistor first node is a source, said first transistor second node is a drain, and said first transistor control node is a gate;
said second transistor first node is a source, said second transistor second node is a drain, and said second transistor control node is a gate; and
said third transistor first node is a source, said third transistor second node is a drain, and said third transistor control node is a gate.
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9. The buffer of claim 1, wherein said second predetermined voltage node is connectable to a ground node.
Specification