Charge pump circuit, passive buffer that employs the charge pump circuit, and pass gate that employs the charge pump circuit

• US 20040150009A1
• Filed: 01/31/2003
• Published: 08/05/2004
• Est. Priority Date: 01/31/2003
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Erickson, Ian, Cogdill, Michael H., Marshall, David John
• Granted Patent: US 6,825,699 B2
• Time in Patent Office: Days
• US Class Current: 257/207
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

Buffer that includes an input node, an output node, and a three-transistor charge pump circuit is coupled to the input node and the output node. The buffer generates an output signal that is a delayed version of a signal presented at the input node. The three-transistor charge pump includes a first transistor (e.g., a pass transistor) that includes a drain electrode that is coupled to the input node, a gate electrode and a source electrode; a second transistor that includes a drain electrode that is coupled to a first predetermined voltage, a gate electrode coupled to the drain electrode of the second transistor, and a source electrode coupled to the gate electrode of the first transistor; and a capacitive element that includes a first electrode that is coupled to the source electrode of the second transistor and the gate electrode of the first transistor and a second electrode that is coupled to the output node.

Claims

1. A buffer comprising:

a) an input node;

b) an output node; and

c) a three-transistor charge pump circuit coupled to the input node and the output node for generating an output signal delaying a signal presented at the input node.

2. The buffer of claim 1 wherein the three-transistor charge pump includes

a first transistor that includes a drain electrode that is coupled to the input node, a gate electrode and a source electrode;

a second transistor that includes a drain electrode that is coupled to a first predetermined voltage, a gate electrode coupled to the drain electrode of the second transistor, and a source electrode coupled to the gate electrode of the first transistor; and

a capacitive element that includes a first electrode that is coupled to the source electrode of the second transistor and the gate electrode of the first transistor and a second electrode that is coupled to the output node.

3. The buffer of claim 2 wherein the capacitive element includes a third transistor that includes a drain electrode, a source electrode coupled to the drain electrode and the output node, and a gate electrode coupled to the gate of the first transistor.

4. The buffer of claim 2 wherein the first transistor, the second transistor, and the third transistor are all n-type field effect transistors (n-FETs).

5. The buffer of claim 2 wherein the first transistor, the second transistor, and the third transistor are all p-type field effect transistors (p-FETs).

6. The buffer of claim 1 wherein the buffer is a full logic level passive buffer.

7. The buffer of claim 2 wherein the first predetermined voltage is a V_DD voltage.

8. A pass gate comprising:

a) an input node;

b) an output node;

c) a charge pump circuit coupled to the input node and the output node including a pass transistor; and

d) a control transistor coupled to the charge pump circuit for receiving a control signal and based thereon for selectively enabling the charge pump circuit to pass the signal a the input node to the output node;

wherein the charge pump circuit selectively increases the gate voltage of the pass transistor based on the output of the control signal.

9. The pass gate of claim 8 wherein the charge pump circuit includes

a first transistor that includes a drain electrode that is coupled to the input node, a gate electrode and a source electrode;

a second transistor that includes a drain electrode that is coupled to a first predetermined voltage, a gate electrode coupled to the drain electrode of the second transistor, and a source electrode coupled to the gate electrode of the first transistor;

a capacitive element that includes a first electrode that is coupled to the source electrode of the second transistor and the gate electrode of the first transistor and a second electrode that is coupled to the output node; and

wherein the control transistor includes a drain electrode coupled to the first electrode of the capacitive element, a gate electrode for receiving the control signal, and a source electrode coupled to a second predetermined voltage.

10. The pass gate of claim 9 wherein the capacitive element includes a third transistor that includes a drain electrode, a source electrode coupled to the drain electrode and the output node, and a gate electrode coupled to the gate of the first transistor.

11. The pass gate of claim 9 wherein the first transistor, the second transistor, the third transistor, and the control transistor are all n-type field effect transistors (n-FETs).

12. The pass gate of claim 9 wherein the first transistor, the second transistor, the third transistor, and the control transistor are all p-type field effect transistors (p-FETs).

13. The pass gate of claim 8 wherein the gate is a full logic level pass gate.

14. The pass gate of claim 8 wherein the first predetermined voltage is a V_DD voltage.

15. The pass gate of claim 8 wherein the second predetermined voltage is a GND voltage.