Semiconductor device and method for fabricating the same

• US 6,861,703 B2
• Filed: 09/09/2003
• Issued: 03/01/2005
• Est. Priority Date: 12/25/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Inagawa, Hiroshi, Machida, Nobuo, Ooishi, Kentaro
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US10/657,246
• Publication Number:
  US 20040046190A1
• Time in Patent Office: 539 Days
• Field of Search: 257328-334
• US Class Current: 257/330
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Claims

1. A semiconductor device including a MISFET, comprising:

a semiconductor substrate having a first conduction type;

a first semiconductor region having the first conduction type, formed in the semiconductor substrate;

a second semiconductor region having a second conduction type which is opposite to the first conduction type, formed over the first semiconductor region;

a third semiconductor region having the first conduction type, formed over the second semiconductor region;

an insulating film formed over the third semiconductor region;

a first hole reaching the second semiconductor region, formed in the third semiconductor region;

a second hole connected to the first hole, formed in the insulating film; and

a conductive film formed in the first and the second holes,

wherein the conductive film is electrically connected to the second and the third semiconductor regions,

a width of the second hole is larger than a width of the first hole,

the semiconductor substrate has a main surface and a back surface,

a trench reaching the first semiconductor region is formed in the main surface of the semiconductor substrate,

a gate insulating film of the MISFET is formed in the trench, and

a gate electrode of the MISFET is formed over the gate insulating film.

2. The semiconductor device according to claim 1, wherein:

the conductive layer in the second hole and the third semiconductor region are contacted at an upper surface and a side surface of the third semiconductor region.

3. The semiconductor device according to claim 1, wherein:

the first, the second, and the third semiconductor regions comprise a drain region, a channel-forming region, and a source region of the MISFET, respectively.

4. The semiconductor device according to claim 3, wherein:

the conductive layer in the second hole and the source region are contacted at an upper surface and a side surface of the source region.

5. A semiconductor device including a MISFET, comprising:

a first semiconductor region having a first conductive type and formed in a semiconductor substrate;

a second semiconductor region having a second conductive type opposite to said first conductive type and formed over said first semiconductor region;

a third semiconductor region having said first conductive type and formed over said second semiconductor region;

a first opening reaching said second semiconductor region and formed in said third semiconductor region such that said first opening exposes a side surface of said third semiconductor region;

a fourth semiconductor region of said second conductivity type formed in said second semiconductor region and formed in self-alignment with said first opening such that an impurity concentration of said fourth semiconductor region is greater than that of said second semiconductor region and such that said first opening exposes said fourth semiconductor region; and

an insulating film formed over said third semiconductor region and having a second opening,

wherein said second opening has a width greater than that of said first opening such that said second opening exposes an upper surface of said third semiconductor region and said first opening, and

a conductive film is formed in said first opening and said second opening and electrically connected to said third semiconductor region and said fourth semiconductor region such that said conductive film is electrically connected to said upper surface of said third semiconductor region.

6. A semiconductor device according to claim 5, further comprising:

a trench formed in said first semiconductor region, said second semiconductor region and third semiconductor region;

a gate insulating film of said MISFET formed on a side surface of said trench; and

a gate electrode of said MISFET formed on said gate insulating film such that said gate electrode is buried in said trench,

wherein said first semiconductor region serves as a drain region of said MISFET, and

wherein said third semiconductor region serves as a source region of said MISFET.

7. A semiconductor device according to claim 6, wherein said fourth semiconductor region does not contact said trench.

8. A semiconductor device including a MISFET, comprising:

a first semiconductor region having a first conductive type and formed in a semiconductor substrate;

a second semiconductor region having a second conductive type opposite to said first conductive type and formed over said first semiconductor region;

a third semiconductor region having said first conductive type and formed over said second semiconductor region;

a first opening reaching said second semiconductor region and formed in said third semiconductor region such that said first opening exposes a Bide surface of said third semiconductor region;

a fourth semiconductor region of said second conductivity type formed in said second semiconductor region and formed in self-alignment with said first opening such that an impurity concentration of said fourth semiconductor region is greater than that of said second semiconductor region and such that said first opening exposes said fourth semiconductor region;

a conductive film formed in said first opening and electrically connected to said third semiconductor region and said fourth semiconductor region such that said conductive film is electrically connected to said upper surface of said third semiconductor region;

a trench formed in said first semiconductor region, said second semiconductor region and said third semiconductor region;

a gate insulating film of said MISFET formed on a side surface of said trench; and

a gate electrode of said MISFET formed on said gate insulating film such that said gate electrode is buried in said trench,

wherein said first semiconductor region serves as a drain region of said MISFET, and

wherein said third semiconductor region serves as a source region of said MISFET.

9. A semiconductor device according to claim 8, wherein said fourth semiconductor region does not contact said trench.