Method of forming a thin film transistor substrate with a interconnection electrode

• US 6,887,744 B2
• Filed: 12/09/2002
• Issued: 05/03/2005
• Est. Priority Date: 12/18/2001
• Status: Expired due to Term

• Current Assignee: Unified Innovative Technology, LLC
• Original Assignee: Fujitsu Display Technologies Corporation (Fujitsu Limited)
• Inventors: Hotta, Kazushige
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US10/314,892
• Publication Number:
  US 20030153110A1
• Time in Patent Office: 876 Days
• Field of Search: 438/97, 438/98, 438/149, 438/151, 438/166, 438/488, 438/597, 438/652, 438/666
• US Class Current: 438/151
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

A thin film transistor substrate including a semiconductor layer having a source region and a drain region, an insulating film and a gate electrode which are formed on the semiconductor layer, an interlayer insulating film which is a film stack with mutually different dielectric constants and which covers the gate electrode, a source region contact hole and a drain region contact hole which are formed on the interlayer insulating film, a pixel electrode connected to the source region through the source region contact hole, a first conductive film connected to the drain region through the drain region contact hole and formed of the same film as that of the pixel electrode, and a second conductive film connected to the drain region through the first conductive film.

Claims

1. A method of manufacturing a thin film transistor substrate comprising the steps of:

forming a pattern of a semiconductor layer on or above an insulating substrate;

forming a gate insulating film on the semiconductor layer;

forming a gate electrode on the gate insulating film;

introducing impurities into portions of the semiconductor layer, which are to be a source region and a drain region;

forming an interlayer insulating film including a plurality of insulating films with mutually different dielectric constants on the semiconductor layer and the gate electrode;

forming contact holes in portions of the interlayer insulating film, the portions being at least on the source region and the drain region;

forming a transparent conductive film on the interlayer insulating film and inner surfaces of the contact holes;

forming a metal film on the transparent conductive film;

forming a interconnection electrode in a portion including the contact hole of the drain region by patterning the metal film while using the transparent conductive film as an etch stop layer; and

forming a pixel electrode connected to the source region through the contact hole and forming the interconnection electrode connected to the drain region through the transparent conductive film in the contact hole by patterning the transparent conductive film.

2. A method of manufacturing a thin film transistor substrate comprising the steps of:

forming a pattern of a semiconductor layer on or above an insulating substrate;

forming a gate insulating film on the semiconductor layer;

forming a gate electrode on the gate insulating film;

introducing impurities into portions of the semiconductor layer, which are to be a source region and a drain region;

forming an interlayer insulating film including a plurality of insulating films with mutually different dielectric constants on the semiconductor layer and the gate electrode;

forming contact holes in portions of the interlayer insulating film, the portions being at least on the source region and the drain region;

forming a transparent conductive film on the interlayer insulating film and inner surfaces of the contact holes;

forming a metal film on the transparent conductive film;

forming a pattern of a resist film on the metal film so that a thickness of a portion for a formation of a pixel electrode connected with the source region is thinner than a thickness of a portion for a formation of a interconnection electrode connected with the drain region;

forming the interconnection electrode by etching the metal film and the transparent conductive film while using the resist film as a mask;

selectively removing the portion of the resist film for the formation of the pixel electrode and leaving the portion of the resist film for the formation of the interconnection electrode; and

forming the pixel electrode by etching a portion of the metal film where the pixel electrode is formed while using the portion of the resist film for the formation of the interconnection electrode as a mask and using the transparent conductive film as an etch stop layer.

3. A method of manufacturing a thin film transistor substrate, comprising the steps of:

forming patterns of a semiconductor layer for a one conductivity type channel transistor and a semiconductor layer for a opposite conductivity type channel transistor on or above an insulating substrate;

forming a gate insulating film on the semiconductor layers;

forming a conductive film, which is to be gate electrodes, on the gate insulating film;

forming a structure in which a gate insulating film for the opposite conductivity type channel transistor and the gate electrode for the opposite conductivity type channel transistor, the gate electrode having a narrower width than a width of the gate insulating film for the opposite conductivity type channel transistor, are stacked from bottom to top on the semiconductor layer for the opposite conductivity type channel transistor, and forming a pattern of a covering film stack in which a gate insulating film and a conductive film are stacked, the covering film stack covering all of the semiconductor layer for the one conductivity type channel transistor, by patterning the conductive film and the gate insulating film;

forming predetermined source and drain regions for the opposite conductivity type channel transistor by introducing impurities of the opposite conductivity type into the semiconductor layer for the opposite conductivity type channel transistor while using at least anyone of the gate electrode for the opposite conductivity type channel transistor and the gate insulating film therefore as a mask;

forming a structure in which a gate insulating film for the one conductivity type channel transistor and the gate electrode for the one conductivity type channel transistor, the gate electrode having a narrower width than a width of the gate insulating film for the one conductivity type channel transistor, are stacked from bottom to top, by patterning the covering film stack; and

forming predetermined source and drain regions for the one conductivity type channel transistor by introducing impurities of the one conductivity type into the semiconductor layer for the one conductivity type channel transistor while using at least anyone of the gate electrode for the one conductivity type channel transistor and the gate insulating film therefor as a mask.

4. A method of manufacturing a thin film transistor substrate comprising the steps of:

forming patterns of a semiconductor layer for a one conductivity type channel transistor and a semiconductor layer for a opposite conductivity type channel transistor on or above an insulating substrate;

forming a gate insulating film on the semiconductor layers;

forming a conductive film, which is to be gate electrodes, on the gate insulating film;

forming the gate electrode for the opposite conductivity type channel transistor on the semiconductor layer for the opposite conductivity type channel transistor, and forming a pattern of a covering conductive film which covers all of the semiconductor layer for the one conductivity type channel transistor by patterning the conductive film;

forming a source region and a drain region for the opposite conductivity type channel transistor by introducing impurities of the opposite conductivity type into the semiconductor layer for the opposite conductivity type channel transistor through the gate insulating film while using the gate electrode for the opposite conductivity type channel transistor as a mask;

forming a structure in which a gate insulating film for the one conductivity type channel transistor and the gate electrode for the one conductivity type channel transistor, the gate electrode having a narrower width than a width of the gate insulating film for the one conductivity type channel transistor, are stacked from bottom to top, by patterning the covering conductive film and the gate insulating film; and

forming predetermined source and drain regions for the one conductivity type channel transistor, by introducing impurities of the one conductivity type into the semiconductor layer for the one conductivity type channel transistor while using at least anyone of the gate electrode for the one conductivity type channel transistor and the gate insulating film therefor as a mask.

5. A method of manufacturing a thin film transistor substrate comprising the steps of:

forming patterns of a semiconductor layer for a one conductivity type channel transistor and a semiconductor layer for a opposite conductivity type channel transistor on or above an insulating substrate;

forming a gate insulating film on the semiconductor layers;

forming a conductive film, which is to be gate electrodes, on the gate insulating film;

forming a structure in which a gate insulating film for the one conductivity type channel transistor and the gate electrode for the one conductivity type channel transistor having a narrower width than a width of the gate insulating film for the one conductivity type channel transistor are stacked from bottom to top on the semiconductor layer for the one conductivity type channel transistor, and forming a pattern of a covering film stack in which a gate insulating film and a conductive film are stacked, the covering film stack covering all of the semiconductor layer for the opposite conductivity type channel transistor, by patterning the conductive film and the gate insulating film;

forming a source region and a drain region for the one conductivity type channel transistor by introducing impurities of the one conductivity type into the semiconductor layer for the one conductivity type channel transistor while using at least anyone of the gate electrode for the one conductivity type channel transistor and the gate insulating film therefore as a mask;

patterning a resist film delimiting a region for forming the gate electrode for the opposite conductivity type channel transistor on the covering film stack and covering the semiconductor layer for the one conductivity type channel transistor and the gate electrode therefore;

forming the gate electrode for the opposite conductivity type channel transistor, the gate electrode having a predetermined width equal to or wider than a width of the resist film by etching the covering film stack while using the resist film as a mask; and

forming source and drain regions for the opposite conductivity type channel transistor by introducing impurities of the opposite conductivity type into the semiconductor layer for the opposite conductivity type channel transistor while using at least anyone of the resist film and the gate electrode for the opposite conductivity type channel transistor as a mask.