Memory array employing single three-terminal non-volatile storage elements

• US 6,894,916 B2
• Filed: 09/27/2002
• Issued: 05/17/2005
• Est. Priority Date: 09/27/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Reohr, William Robert, Wang, Li-Kong
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Hur, J. H.
• Application Number:
  US10/256,715
• Publication Number:
  US 20040062075A1
• Time in Patent Office: 963 Days
• Field of Search: 365/148, 365/145, 365/65, 365/67, 365/100
• US Class Current: 365/148
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

An improved non-volatile memory array comprises a plurality of memory cells, at least one of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell. The memory array further comprises a plurality of write lines operatively coupled to the memory cells for selectively writing the logical state of one or more memory cells in the memory array, and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing the logical state of one or more memory cells in the memory array. The memory array is advantageously configured so as to eliminate the need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell.

Claims

1. A non-volatile memory array, comprising:

a plurality of memory cells, each of at least a portion of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the memory cell, the non-volatile storage element having a gate terminal, a first drain/source terminal and a second drain/source terminal, the non-volatile storage element comprising a ferroelectric gate field-effect transistor (FeGFET);

a plurality of write lines operatively coupled to the gate terminals of corresponding non-volatile storage elements in the memory cells for selectively writing one or more memory cells in the memory array; and

a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing one or more memory cells in the memory array;

wherein the write lines are arranged such that no two memory cells coupled to a same write line share a same word line or a same bit line, and wherein the memory array is configured so as to eliminate a need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell;

wherein each of at least a portion of the memory cells is selectively operable in at least a first mode, wherein a logical state of the at least one memory cell is read, and a second mode, wherein the at least one memory cell is written to a predetermined logical state, the second mode comprising;

(i) applying a first voltage to the first drain/source terminal of the FeGFET and applying a second voltage to the second drain/source terminal of the FeGFET, the first voltage and the second voltage being substantially equal to one another; and

(ii) applying a third voltage to the gate terminal of the FeGFET, the third voltage having a magnitude and polarity which, when summed with the first voltage or the second voltage, results in a voltage potential at least equal to a coercive voltage V_C of a ferroelectric sate dielectric layer in the FeGFET.

2. The memory array of claim 1, wherein:

the word lines are arranged substantially orthogonal to the bit lines; and

the write lines are arranged substantially diagonal with respect to the word lines and bit lines.

3. The memory array of claim 1, wherein each of at least a portion of the memory cells is operatively coupled at an intersection of a bit line and a corresponding word line.

4. The memory array of claim 1, wherein the first drain/source terminal of the non-volatile storage element is coupled to a corresponding word line and the second drain/source terminal of the non-volatile storage element is coupled to a corresponding bit line.

5. The memory array of claim 1, wherein the first mode of operation comprises determining a conductance of a region between the first and second drain/source terminals of the non-volatile storage element, the conductance being representative of the logical state of the at least one memory cell.

6. The memory array of claim 5, wherein during the first mode of operation, the conductance of the region between the first and second drain/source terminals in the non-volatile storage element is determined by performing at least one of:

applying a predetermined voltage potential across the first and second drain/source terminals of the non-volatile storage element and substantially concurrently measuring a current flowing through the region between the first and second drain/source terminals of the non-volatile storage element; and

applying a predetermined current through the region between the first and second drain/source terminals of the non-volatile storage element and substantially concurrently measuring a voltage across the first and second drain/source terminals of the non-volatile storage element.

7. The memory array of claim 1, wherein during the second mode of operation, the logical state of the at least one memory cell is written by applying a voltage potential between the gate terminal of the FeGFET and at least one of the first and second drain/source terminals of the FeGFET, such that an electric field is generated in a ferroelectric gate dielectric layer in the FeGFET which is at least equal to a coercive field associated with the ferroelectric gate dielectric layer, whereby the logical state of the memory cell is stored in the FeGFET, the logical state being determined at least in part by a direction of the electric field.

8. The memory array of claim 1, wherein the first voltage has a potential substantially equal to one-half of the coercive voltage (V_C/2), and the third voltage has a potential substantially equal to one-half the coercive voltage and a polarity which is opposite a polarity of the first voltage (−

V_C/2).

9. The memory array of claim 1, wherein each of at least a portion of the memory cells is further selectively operable in at least a third mode, wherein voltage potentials at the gate terminal, the first drain/source terminal and the second of the non-volatile storage element are substantially equal to one another, thereby maintaining the logical state of the at least one memory cell.

10. The memory array of claim 1, wherein at least two memory cells are stacked on top of one another in a vertical dimension.

11. A method of forming a non-volatile memory array, comprising the steps of:

providing a plurality of memory cells, each of at least a portion of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the memory cell, the non-volatile storage element having a gate terminal, a first drain/source terminal and a second drain/source terminal, the non-volatile storage element comprising a ferroelectric gate field-effect transistor (FeGFET);

coupling the memory cells to a plurality of write lines, bit lines and word lines for selectively reading and writing the logical state of one or more memory cells in the memory array, the memory cells being operatively coupled to the write lines, bit lines and word lines so as to eliminate a need for a pass gate being coupled to a corresponding non-volatile storage element in the at least one memory cell, the write lines being arranged such that no two memory cells coupled to a same write line share a same word line or a same bit line;

during a first mode of operation, selectively reading a logical state of at least one memory cell; and

during a second mode of operation, selectively writing a logical state of at least one memory cell;

wherein the step of writing the logical state of the at least one memory cell comprises;

applying a first voltage to the first drain/source terminal of the FeGFET and applying a second voltage to the second drain/source terminal of the FeGFET, the first voltage and the second voltage being substantially equal to one another; and

applying a third voltage to the gate terminal of the FeGFET, the third voltage having a magnitude and polarity which, when summed with the first voltage or the second voltage, results in a voltage potential across a ferroelectric gate dielectric layer in the FeGFET at least equal to a coercive voltage V_C of the ferroelectric gate dielectric layer.

12. The method of claim 11, wherein the step of coupling the memory cells to the plurality of write lines, bit lines and word lines comprises:

connecting the first drain/source terminal of each non-volatile storage element to a corresponding word line; and

connecting the second drain/source terminal of each non-volatile storage element to a corresponding bit line.

13. The method of claim 11, further comprising the steps of:

arranging at least a portion of the plurality of word lines to be substantially orthogonal to at least a portion of the plurality of bit lines; and

arranging at least a portion of the plurality of write lines to be substantially diagonal with respect to the word and bit lines.

14. The method of claim 11, wherein the step of reading the logical state of the at least one memory cell comprises determining a conductance of a channel region between the first and second drain/source terminals of the non-volatile storage element, the conductance being representative of the logical state of the at least one memory cell.

15. The method of claim 14, wherein the step of determining the conductance of the channel region comprises at least one of:

applying a predetermined voltage potential across the first and second drain/source terminals of the non-volatile storage element and substantially concurrently measuring a current flowing through the channel region between the first and second drain/source terminals of the non-volatile storage element; and

applying a predetermined current through the channel region between the first and second drain/source terminals of the non-volatile storage element and substantially concurrently measuring a voltage across the first and second drain/source terminals of the non-volatile storage element.

16. The method of claim 11, wherein the step of writing the logical state of the at least one memory cell comprises generating an electric field in a ferroelectric gate dielectric layer in the FeGFET which is at least equal to a coercive field associated with the ferroelectric gate dielectric layer, whereby the logical state of the memory cell is stored in the FeGFET, the logical state being determined at least in part by a direction of the electric field.

17. The method of claim 11, wherein the first voltage has a potential substantially equal to one-half of the coercive voltage (V_C/2), and the third voltage has a potential substantially equal to one-half the coercive voltage and a polarity which is opposite a polarity of the first voltage (−

V_C/2).

18. The method of claim 11, further comprising the step of stacking two or more memory cells on top of one another in a vertical dimension.