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Circuits and methods for screening for defective memory cells in semiconductor memory devices

  • US 6,901,014 B2
  • Filed: 05/27/2003
  • Issued: 05/31/2005
  • Est. Priority Date: 05/27/2002
  • Status: Expired due to Fees
First Claim
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1. A semiconductor memory device comprising:

  • a power supply voltage;

    a memory cell;

    a first driver for supplying the power supply voltage to the memory cell in response to a cell power control signal;

    a second driver for supplying a voltage lower than the power supply voltage to the memory cell in response to a cell power down signal; and

    a control circuit for generating the cell power control signal, the control circuit comprising;

    a first test pad;

    a second test pad;

    a cell power control circuit for setting a cell power-off mode in response to an input from the second test pad;

    a first gate circuit for receiving an output of the cell power control circuit and the input from the second pad; and

    a second gate circuit for generating the cell power control signal in response to an output of the first gate circuit and an input from the first test pad.

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