Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region

• US 6,913,964 B2
• Filed: 09/30/2003
• Issued: 07/05/2005
• Est. Priority Date: 03/11/2002
• Status: Expired due to Fees

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Monolithic System Technology
• Inventors: Hsu, Fu-Chieh
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/676,695
• Publication Number:
  US 20040061148A1
• Time in Patent Office: 644 Days
• Field of Search: 438238-239, 438/386
• US Class Current: 438/239
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.

Claims

1. A method of fabricating a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell, the method comprising:

forming a buried region having a first conductivity type below an upper surface of a semiconductor region of a semiconductor substrate, the semiconductor region having a second conductivity type, opposite the first conductivity type; and

forming a field-effect transistor in the semiconductor region over the buried region, the field effect transistor having a source and a drain, wherein the buried region, the source and the drain are formed such that a depletion region is located between the buried region, the source and the drain, the depletion region defining a floating body region of the field effect transistor, and providing the sole lateral isolation for portions of the floating body region.

2. The method of claim 1, wherein the buried region is formed by an ion implantation step.

3. The method of claim 2, wherein the buried region is implanted through a first mask.

4. The method of claim 3, further comprising performing a threshold voltage adjustment implant having the second conductivity type through the first mask.

5. The method of claim 1, further comprising forming one or more shallow trench isolation regions that extend a first depth into the semiconductor substrate.

6. The method of claim 5, further comprising implanting the buried region such that the buried region has a top interface located at or above the first depth in the semiconductor substrate, and a bottom interface located below the first depth in the semiconductor substrate.

7. The method of claim 1, wherein the field-effect transistor is fabricated using a process compatible with a standard CMOS process.

8. The method of claim 1, further comprising forming a well region having the first conductivity type in the semiconductor substrate, wherein the buried region contacts the well region.

9. The method of claim 1, further comprising forming a deep well region having the first conductivity type in the semiconductor substrate, wherein the deep well region is located below and continuous with the buried region.

10. The method of claim 9, further comprising forming a well region having the first conductivity type in the semiconductor substrate, wherein the well region contacts the deep well region.

11. A method of fabricating a plurality of one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cells, the method comprising:

forming a buried region having a first conductivity type below an upper surface of a semiconductor region of a semiconductor substrate, the semiconductor region having a second conductivity type, opposite the first conductivity type; and

forming a plurality of rows of field-effect transistors in the semiconductor region over the buried region, each of the field effect transistors having a source and a drain, wherein the buried region, and each source and drain are formed such that a continuous depletion region is located between the buried region and each source and drain, the depletion region defining floating body regions of the field effect transistors, and providing lateral isolation for floating body regions located in adjacent rows.

12. The method of claim 11, wherein the step of forming a plurality of rows of field-effect transistors comprises forming a plurality of word lines, wherein each of the word lines is associated with a corresponding row of the field effect transistors.

13. The method of claim 11, wherein the buried region is formed by an ion implantation step.

14. The method of claim 13, wherein the buried region is implanted through a first mask.

15. The method of claim 14, further comprising performing a threshold voltage adjustment implant having the second conductivity type through the first mask.

16. The method of claim 11, further comprising forming one or more shallow trench isolation regions that extend a first depth into the semiconductor substrate, wherein the shallow trench isolation regions provide lateral isolation for field effect transistors located in the same row.

17. The method of claim 16, further comprising implanting the buried region such that the buried region has a top interface located at or above the first depth in the semiconductor substrate, and a bottom interface located below the first depth in the semiconductor substrate.

18. The method of claim 11, wherein the field-effect transistors are fabricated using a process compatible with a standard CMOS process.

19. The method of claim 11, further comprising forming a well region having the first conductivity type in the semiconductor substrate, wherein the buried region contacts the well region.

20. The method of claim 11, further comprising forming a deep well region having the first conductivity type in the semiconductor substrate, wherein the deep well region is located below and continuous with the buried region.

21. The method of claim 20, further comprising forming a well region having the first conductivity type in the semiconductor substrate, wherein the well region contacts the deep well region.