Highly compact EPROM and flash EEPROM devices

• US 6,914,817 B2
• Filed: 02/11/2003
• Issued: 07/05/2005
• Est. Priority Date: 06/08/1988
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/365,686
• Publication Number:
  US 20030218920A1
• Time in Patent Office: 875 Days
• Field of Search: 365/185.18, 365/185.19, 365/185.21, 365/185.22, 365/185.23, 365/185.24
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 438/964 : Roughened surface

Abstract

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. For an array of electrically alterable memory cells divided into blocks of cells that are re-settable together to a starting state and having means for addressing individual cells within said blocks to program and read their states, said memory cells individually including a field effect transistor having a threshold voltage level that is variable in accordance with an amount of net charge stored therein, a method of operating the array, comprising the steps of:

establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of detectable states of the individual cells in excess of two,

programming the effective threshold voltage level of at least one addressed cell within one of said blocks from a starting level to one of the plurality of effective threshold voltage levels by altering the amount of charge stored in said at least one addressed cell until the effective threshold voltage of said at least one addressed cell is substantially equal to one of said plurality of effective threshold voltage levels, wherein the state of said at least one addressed cell is set to one of said plurality of states by a method comprising;

applying a given voltage to said addressed cell for a predetermined time sufficient to move the effective threshold voltage level of the addressed cell from the starting level toward said one of the plurality of threshold voltage levels,

thereafter reading an electrical parameter of the addressed cell to determine whether the effective threshold voltage of the addressed cell has reached said of the plurality of threshold voltage levels, and

repeating the voltage applying and reading steps until it is detected by reading step that the effective threshold voltage of the addressed cell has been set to said one of the plurality of threshold voltage levels,

reading the states of the memory cells of individual blocks with the assistance of an error correction scheme that can tolerate a number X of bad cells, and

applying erase conditions to the memory cells of individual blocks until a number of cells N remaining unerased is equal to or less than X.

2. The method according to claim 1, wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels.

3. The method according to claim 1, wherein at least two of the plurality of effective threshold voltage levels in excess of two result from a net positive charge the individual cells.