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Highly compact EPROM and flash EEPROM devices

  • US 6,914,817 B2
  • Filed: 02/11/2003
  • Issued: 07/05/2005
  • Est. Priority Date: 06/08/1988
  • Status: Expired due to Fees
First Claim
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1. For an array of electrically alterable memory cells divided into blocks of cells that are re-settable together to a starting state and having means for addressing individual cells within said blocks to program and read their states, said memory cells individually including a field effect transistor having a threshold voltage level that is variable in accordance with an amount of net charge stored therein, a method of operating the array, comprising the steps of:

  • establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of detectable states of the individual cells in excess of two, programming the effective threshold voltage level of at least one addressed cell within one of said blocks from a starting level to one of the plurality of effective threshold voltage levels by altering the amount of charge stored in said at least one addressed cell until the effective threshold voltage of said at least one addressed cell is substantially equal to one of said plurality of effective threshold voltage levels, wherein the state of said at least one addressed cell is set to one of said plurality of states by a method comprising;

    applying a given voltage to said addressed cell for a predetermined time sufficient to move the effective threshold voltage level of the addressed cell from the starting level toward said one of the plurality of threshold voltage levels, thereafter reading an electrical parameter of the addressed cell to determine whether the effective threshold voltage of the addressed cell has reached said of the plurality of threshold voltage levels, and repeating the voltage applying and reading steps until it is detected by reading step that the effective threshold voltage of the addressed cell has been set to said one of the plurality of threshold voltage levels, reading the states of the memory cells of individual blocks with the assistance of an error correction scheme that can tolerate a number X of bad cells, and applying erase conditions to the memory cells of individual blocks until a number of cells N remaining unerased is equal to or less than X.

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