Memory device, circuits and methods for operating a memory device
First Claim
1. A method of operating a memory device, comprising:
- biasing the memory device from a power source;
determining data of the memory device; and
during at least a portion of the determining, decoupling the power source.
2 Assignments
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Accused Products
Abstract
A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.
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Citations
41 Claims
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1. A method of operating a memory device, comprising:
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biasing the memory device from a power source;
determining data of the memory device; and
during at least a portion of the determining, decoupling the power source. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of reading a ferroelectric memory device, comprising:
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sensing a signal of a ferroelectric cell of the ferroelectric memory device; and
decoupling a power source associated with providing power to the ferroelectric memory device during at least a portion of the sensing. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A memory device comprising:
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a memory cell;
a read circuit to read a state of the memory cell;
a supply node to receive power for operating the memory device;
a transistor comprising a controllable channel electrically disposed in series with the supply node and a control terminal to receive a control signal to affect the controllable channel; and
a controller responsive to a read request to establish a control signal for the transistor and to enable the read circuit to read the memory cell. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A data processing system comprising:
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a processor;
a bus coupled to the processor;
a ferroelectric memory coupled to the bus, the memory to provide data responsive to a read request;
supplies to power the memory; and
isolation circuitry to isolate the ferroelectric memory from at least one supply of the supplies responsive to an isolation request. - View Dependent Claims (38, 39, 40, 41)
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Specification