Memory device, circuits and methods for operating a memory device

• US 6,920,060 B2
• Filed: 08/14/2002
• Issued: 07/19/2005
• Est. Priority Date: 08/14/2002
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Willassen, Trygve, Chow, David GenLong, Dahl, Hans Ola
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/218,396
• Publication Number:
  US 20040032759A1
• Time in Patent Office: 1,070 Days
• Field of Search: 365/145, 365/149, 365/207, 365/209, 365/171, 365/173
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 29/026 in sense amplifiers

Abstract

A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Claims

1. A method of operating a memory device, comprising:

biasing the memory device from a power source;

determining data of the memory device; and

during at least a portion of the determining, decoupling the power source.

2. A method according to claim 1, in which the determining data comprises sensing a signal related to a condition of at least one memory cell of a plurality of memory cells of the memory device.

3. A method according to claim 1, in which the determining data comprises sensing a charge release from at least one ferroelectric memory cell of a plurality of ferroelectric memory cells of the memory device.

4. A method according to claim 1, in which the determining data comprises sensing a difference between a signal provided by at least one ferroelectric memory cell of the memory device relative to that of at least one reference ferroelectric cell of the memory device.

5. A method according to claim 4, in which the determining data further comprises:

biasing a first electrode of the at least one ferroelectric memory cell using a first voltage source;

biasing a first electrode of the at least one reference ferroelectric cell using the first voltage source; and

transitioning a voltage level of second electrodes of the at least one ferroelectric memory cell and the at least one reference ferroelectric cell to change their bias levels from quiescent levels to read levels;

the sensing comprises providing the sensing over a duration having an interval after the start of the transitioning of the voltage levels; and

the decoupling comprises electrically isolating the first voltage source from the first electrodes of respective ferroelectric memory and reference cells.

6. A method according to claim 5, in which the isolating the first voltage source is provided during the sensing the difference between the signals.

7. A method according to claim 6, in which the isolating the first voltage is maintained through the duration of the sensing the difference between the signals.

8. A method according to claim 5, in which the decoupling further comprises electrically isolating voltage sources associated with ferroelectric memory cells other than the at least one ferroelectric memory cell.

9. A method according to claim 1, in which

the biasing of the memory device comprises biasing a plurality of ferroelectric memory cells of the memory device with quiescent level voltages;

the determining data comprises;

biasing at least one select ferroelectric memory cell of the plurality with read level voltages; and

sensing charge released by the at least one select ferroelectric memory cell; and

the decoupling comprises decoupling at least one voltage source of voltage sources associated with the quiescent and the read level voltages.

10. A method according to claim 9, in which the biasing at least one select ferroelectric memory cell with the read level voltages comprises:

establishing from a first voltage source, a first voltage on a select bitline;

applying from a second voltage source, a second voltage to a select wordline that crosses the select bitline, and

establishing a magnitude of the second voltage relative the first voltage sufficient to affect a polarization state of the select ferroelectric memory cell between the select wordline and the select bitline; and

the decoupling comprises isolating the first voltage source from the select bitline during the sensing of released charge.

11. A method according to claim 10, the sensing of released charge comprising integrating charge propagated by the select bitline relative to that of a reference bitline.

12. A method according to claim 10, the decoupling further comprising isolating the second voltage source from the select wordline during the sensing.

13. A method according to claim 12, the decoupling further comprising electrically isolating wordlines other than the select wordline.

14. A method according to claim 13, the decoupling further comprising electrically isolating bitlines other than the select bitline.

15. A method of reading a ferroelectric memory device, comprising:

sensing a signal of a ferroelectric cell of the ferroelectric memory device; and

decoupling a power source associated with providing power to the ferroelectric memory device during at least a portion of the sensing.

16. A method according to claim 15, in which the decoupling the power source comprises increasing the source resistance of the power source.

17. A method according to claim 15, in which the decoupling the power source comprises adjusting the resistance of a controllable channel in series with a voltage source node associated with receiving a voltage to operate the memory device.

18. A method according to claim 15, in which the decoupling the power source comprises turning-off a gateable transistor having its channel electrically disposed in series with a voltage source node that is to receive power to power the memory device.

19. A method according to claim 15, in which the sensing comprises integrating charge propagated by an active bitline coupled to the ferroelectric memory cell;

and

the decoupling the power source includes electrically isolating the active bitline from the power source.

20. A method according to claim 15, in which the sensing comprises integrating a difference signal related to a difference between the charge propagated by an active bitline that is coupled to the ferroelectric memory cell and the charge propagated by a reference bitline that is coupled to a reference ferroelectric cell, the method further comprising:

precharging the active and reference bitlines with a reference bitline voltage of a bitline voltage source; and

isolating the reference and active bitlines from the bitline voltage source during the integrating.

21. A method according to claim 20, in which the isolating the reference and active bitlines comprises turning-off a transistor electrically disposed in series between the bitline voltage source and a node for sourcing at least the reference bitlines.

22. A method according to claim 20, in which the decoupling the power source comprises increasing the source resistance of the power source.

23. A method according to claim 22, in which the increasing the source resistance comprises turning-off at least one supply access transistor of the memory device that is electrically disposed in series between its power source and the respective circuit for driving at least one of the bitlines and wordlines of the ferroelectric memory device.

24. A method according to claim 23, further comprising starting the integrating after the turning-off of at least one supply access transistor.

25. A memory device comprising:

a memory cell;

a read circuit to read a state of the memory cell;

a supply node to receive power for operating the memory device;

a transistor comprising a controllable channel electrically disposed in series with the supply node and a control terminal to receive a control signal to affect the controllable channel; and

a controller responsive to a read request to establish a control signal for the transistor and to enable the read circuit to read the memory cell.

26. A memory device according to claim 25, in which the controller is responsive to the read request to turn-off the transistor during a portion of a read operation of the read circuit.

27. A memory device according to claim 25, in which the read circuit comprises a sense amplifier responsive to the controller to sense a charge release of the memory cell.

28. A memory device according to claim 27, in which the controller is operable responsive to the read request to turn-off the transistor and to enable the sense amplifier after turning-off the transistor.

29. A memory device according to claim 25, further comprising:

a plurality of bitlines, the memory cell coupled to an active bitline of the plurality;

a plurality of wordlines, the memory cell coupled to an active wordline of the plurality;

a wordline driver circuit to drive the active and other passive wordlines of the plurality with voltages of respective wordline voltage sources;

the transistor associated with a wordline voltage and having its controllable channel electrically disposed in series with the supply line between the wordline driver circuit and a supply node of one of the wordline voltage sources.

30. A memory device according to claim 29, further comprising a decoupling capacitor coupled to the supply line between the wordline driver circuit and the transistor.

31. A memory device according to claim 30, in which the memory cell comprises a

ferroelectric memory cell;

and

the memory device further comprises a bitline driver circuit to drive the active and other passive bitlines of the plurality with voltages of respective bitline voltage sources;

another transistor associated with a bitline voltage and comprising a controllable channel disposed in series with the supply line between the bitline driver circuit and a supply nodes of one of the bitline voltage sources.

32. A memory device according to claim 31, further comprising a decoupling capacitor coupled to the supply line between the bitline driver circuit and the another transistor.

33. A memory device according to claim 31, in which the bitline driver circuit comprises a buffer to buffer a bitline reference voltage for availability to the bitlines, the buffer to be powered from a source separate from the bias sources for the wordlines and bitlines.

34. A memory device according to claim 31, further comprising a bitline multiplexer configurable responsive to the controller to couple the active bitline of the plurality to receive the reference voltage of the buffer.

35. A memory device according to claim 34, in which the buffer input is coupled to a reference bitline of the plurality of bitlines.

36. A memory device according to claim 30, in which the capacitor comprises at least one of a semiconductor dopant well and an insulated gate of a MOSFET.

37. A data processing system comprising:

a processor;

a bus coupled to the processor;

a ferroelectric memory coupled to the bus, the memory to provide data responsive to a read request;

supplies to power the memory; and

isolation circuitry to isolate the ferroelectric memory from at least one supply of the supplies responsive to an isolation request.

38. A data processing system according to claim 37, further comprising a read controller to provide an isolation request to the isolation circuitry during a read of the ferroelectric memory.

39. A data processing system according to claim 37, in which the isolation circuitry comprises a transistor electrically disposed between the ferroelectric memory and the at least one voltage supply.

40. A data processing system according to claim 39, in which the isolation circuitry further comprises a decoupling capacitor electrically coupled to a supply node between the transistor and the memory.

41. A data processing system according to claim 39, further comprising:

a read controller to establish a resistance of the transistor responsive to a read request of the ferroelectric memory.