CMOS imager with selectively silicided gate
First Claim
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1. A CMOS imager having improved transistor speed comprising:
- a substrate doped to a first conductivity type;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array.
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Abstract
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.
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Citations
42 Claims
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1. A CMOS imager having improved transistor speed comprising:
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a substrate doped to a first conductivity type;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A processing system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor and including;
a substrate doped to a first conductivity type;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A CMOS imager having improved transistor speed comprising:
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a substrate doped to a first conductivity type;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array, wherein said photogate is void of said deposited opaque conductive layer.
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32. A processing system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor and including;
a substrate doped to a first conductivity type;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array, wherein said photogate is void of said deposited opaque conductive layer.
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33. A CMOS imager having improved transistor speed comprising:
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a substrate; and
an array of pixel cells formed on said substrate, each of said cells including a photogate, a transfer gate, a reset gate, and a partially removed opaque conductive layer, wherein a remaining portion of said opaque conductive layer remains over said transfer gate and said reset gate, and wherein said photogate is void of said opaque conductive layer. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42)
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Specification