High density 3d rail stack arrays and method of making

• US 6,940,109 B2
• Filed: 02/18/2004
• Issued: 09/06/2005
• Est. Priority Date: 06/27/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Patel, Kedar, Walker, Andrew J., Scheuerlein, Roy, Ilkbahar, Alper
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US10/779,760
• Publication Number:
  US 20040159860A1
• Time in Patent Office: 566 Days
• Field of Search: 257/213, 257/71, 257/757, 257/520, 257/751, 257/190, 257/755
• US Class Current: 257/213
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.

Claims

1. A monolithic three dimensional array of field effect transistors, comprising:

(a) a substrate;

(b) a plurality of first rails disposed at a first height relative to the substrate in a first direction, wherein each of the plurality of first rails comprises a first-rail heavily doped semiconductor layer of a first conductivity type;

(c) a plurality of second rails disposed at a second height different from the first height, and in a second direction different from the first direction,

wherein each of the plurality of second rails comprises;

a second-rail lightly doped semiconductor channel layer of a second conductivity type located in contact with the first rails;

a second-rail heavily doped semiconductor layer of the first conductivity type;

a second-rail gate insulating layer between and in contact with the second-rail channel layer and the second-rail heavily doped semiconductor layer of the first conductivity type; and

a second-rail heavily doped semiconductor layer of the second conductivity type electrically connected to the second-rail heavily doped semiconductor layer of the first conductivity type by a second-rail metal or metal silicide layer;

(d) a plurality of third rails disposed in the first direction at a third height relative to the substrate, wherein each of the plurality of third rails comprises;

a third-rail lightly doped semiconductor channel layer of the first conductivity type located in contact with the second-rail heavily doped semiconductor layer of the second conductivity type in the second rails;

a third-rail heavily doped semiconductor layer of the second conductivity type;

a third-rail heavily doped semiconductor layer of the first conductivity type electrically connected to the third-rail heavily doped semiconductor layer of the second conductivity type by a third-rail metal or metal silicide layer; and

a third-rail gate insulating layer between and in contact with the third-rail channel layer and the third-rail heavily doped semiconductor layer of the second conductivity type.

2. The array of claim 1, further comprising a plurality of fourth rails disposed in the second direction at a fourth height relative to the substrate, wherein each of the plurality of fourth rails comprises:

a fourth-rail lightly doped semiconductor channel layer of the second conductivity type in contact with the third-rail heavily doped semiconductor layer of the first conductivity type in the third rails;

a fourth-rail heavily doped semiconductor layer of the first conductivity type;

a fourth-rail gate insulating layer between and in contact with the fourth-rail channel layer and the fourth-rail heavily doped semiconductor layer of the first conductivity type; and

a fourth-rail heavily doped semiconductor layer of the second conductivity type electrically connected to the fourth-rail heavily doped semiconductor layer of the first conductivity type by a fourth-rail metal or metal silicide layer.

3. The array of claim 2, wherein:

the first-rail heavily doped semiconductor layer of the first conductivity type comprises source or a drain regions of a plurality of first transistors;

the second-rail heavily doped semiconductor layer of the first conductivity type comprises gate electrodes of the first transistors;

the second-rail heavily doped semiconductor layer of the second conductivity type comprises source or drain regions of a plurality of second transistors;

the third-rail heavily doped semiconductor layer of the second conductivity type comprises gate electrodes of the second transistors; and

the third-rail heavily doped semiconductor layer of the first conductivity type comprises source or drain regions of a plurality of third transistors.

4.The array of claim 3, wherein;

one or more of the semiconductor layers in the first through fourth rails is a polysilicon layer; and

p1 the pluralities of first, second and third transistors comprise top gate staggered thin film transistors located above an insulating substrate or above an insulating layer formed over a silicon substrate.

4. The array of claim 4, further comprising:

planarized insulating fill located between adjacent first rails, between adjacent second rails, between adjacent third rails, and between adjacent fourth rails;

a first insulating isolation layer located between the first rails and the second rails;

a second insulating isolation layer located between the second rails and the third rails;

a third insulating isolation layer located between the third rails and the fourth rails;

a plurality of first openings in the first isolation layer through which the second-rail lightly doped semiconductor layers of the second conductivity type in the second rails contact the first-rail heavily doped semiconductor layers of the first conductivity type in the first rails;

a plurality of second openings in the second isolation layer through which the third-rail lightly doped semiconductor layers of the first conductivity type in the third rails contact the second-rail heavily doped semiconductor layers of the second conductivity type in the second rails; and

a plurality of third openings in the third isolation layer through which the fourth-rail lightly doped semiconductor layers of the second conductivity type in the fourth rails contact the third-rail heavily doped semiconductor layers of the first conductivity type in the third rails.

5. A semiconductor device, comprising:

a first field effect transistor of a first polarity; and

a second field effect transistor of a second polarity;

wherein a gate electrode of the first transistor is electrically connected to a source or drain of the second transistor without any lateral interconnects.

6. A method of making a monolithic three dimensional field effect transistor array, comprising:

forming a plurality of first rails disposed at a first height relative to a substrate in a first direction, wherein each of the plurality of first rails comprises a first-rail heavily doped semiconductor layer of a first conductivity type;

forming a first insulating isolation layer over the first plurality of rails;

patterning the first isolation layer to form a plurality of first openings exposing upper portions of adjacent first rails;

forming a second-rail lightly doped semiconductor layer of a second conductivity type over the patterned isolation layer such that transistor channel portions in the second-rail lightly doped semiconductor layer of the second conductivity type contact the first-rail heavily doped semiconductor layer of the first conductivity type through the first openings;

forming a second-rail gate insulating layer over the second-rail lightly doped semiconductor layer of the second conductivity type;

forming a second-rail heavily doped semiconductor layer of the first conductivity type over the second-rail gate insulating layer; and

patterning the second-rail heavily doped semiconductor layer of the first conductivity type, the second-rail gate insulating layer, and the second-rail lightly doped semiconductor layer of the second conductivity type to form a plurality of second rails extending in a second direction different from the first direction;

wherein the array comprises;

(a) a substrate;

(b) the plurality of first rails disposed at the first height relative to the substrate in the first direction, wherein each of the plurality of first rails comprises the first-rail heavily doped semiconductor layer of the first conductivity type;

(c) the plurality of second rails disposed at the second height different from the first height, and in the second direction different from the first direction,

wherein each of the plurality of second rails comprises;

the second-rail lightly doned semiconductor channel layer of the second conductiviy type located in contact with the first rails;

the second-rail heavily doned semiconductor layer of the first conductivity type;

the second-rail gate insulating layer between and in contact with the second-rail channel layer and the second-rail heavily doped semiconductor layer of the first conductivity type; and

the second-rail heavily doped semiconductor layer of the second conductivity type electrically connected to the second-rail heavily doped semiconductor layer of the first conductivity type by a second-rail metal or metal silicide layer;

(d) a plurality of third rails disposed in the first direction at a third height relative to the substrate, wherein each of the plurality of third rails comprises;

a third-rail lightly doned semiconductor channel layer of the first conductivity type located in contact with the second-rail heavily doped semiconductor layer of the second conductivity type in the second rails;

a third-rail heavily doped semiconductor layer of the second conductivity type;

a third-rail heavily doped semiconductor layer of the first conductivity type electrically connected to the third-rail heavily doped semiconductor layer of the second conductivity type by a third rail metal or metal silicide layer; and

a third-rail gate insulating layer between and in contact with the third-rail channel layer and the third-rail heavily doped semiconductor layer of the second conductivity type.

7. The method of claim 7, further comprising:

forming a second insulating isolation layer over the plurality of second rails;

patterning the second isolation layer to form a plurality of second openings exposing upper portions of adjacent second rails;

forming the third-rail lightly doped semiconductor layer of the first conductivity type over the patterned second isolation layer such that transistor channel portions of the second-rail lightly doped semiconductor layer contact the second rails through the second openings;

forming the third-rail gate insulating layer over the third-rail lightly doped semiconductor channel layer;

forming the third-rail heavily doped semiconductor layer of the second conductivity type over the third-rail gate insulating layer; and

patterning the third-rail heavily doped semiconductor layer of the second conductivity type, the third-rail gate insulating layer and the third-rail lightly doped semiconductor channel layer to form the plurality of third rails extending in the first direction.

15. The method of claim 7, wherein all layers in the second rails are patterned by etching during one etching step.

8. The method of claim 8, further comprising forming a plurality of fourth rails extending in the second direction in contact with the third rails.

9. The method of claim 8, further comprising:

forming a first insulating fill layer between adjacent first rails;

polishing the first insulating fill layer to expose the first rails using the first rails as a polish stop;

forming a second insulating fill layer between adjacent second rails;

polishing the first insulating fill layer to expose the second rails using the second rails as a polish stop;

forming a third insulating fill layer between adjacent third rails; and

polishing the third insulating fill layer to expose the third rails using the third rails as a polish stop.

11. The method of claim 8, wherein:

the third-rail lightly doped semiconductor channel layer comprises a third-rail lightly doped amorphous silicon or polysilicon layer of the first conductivity type; and

the third-rail heavily doped semiconductor layer of the second conductivity type comprises a third-rail heavily doped polysilicon layer of the second conductivity type formed on the third-rail gate insulating layer.

10. The method of claim 10, wherein the step of forming the first rails further comprises:

forming a first-rail heavily doped polysilicon layer over the substrate;

forming a first-rail metal or metal silicide layer over the first-rail polysilicon layer;

forming the first heavily doped semiconductor layer on the first-rail metal or metal silicide layer; and

patterning the first-rail semiconductor layer and the first-rail polysilicon layer and the first-rail metal or metal silicide layer.

12. The method of claim 12, further comprising:

forming the second-rail metal or metal silicide layer on the second-rail heavily doped semiconductor layer of the first conductivity type;

forming the second-rail heavily doped semiconductor layer of the second conductivity type on the second-rail metal or metal silicide layer;

patterning the second-rail metal or metal silicide layer and the second-rail heavily doped semiconductor layer of the second conductivity type during the step of patterning to form the plurality of second rails;

forming the third-rail metal or metal silicide layer on the third-rail heavily doped polysilicon layer of the second conductivity type;

forming the third-rail heavily doped semiconductor layer of the first conductivity type on the third-rail metal or metal silicide layer; and

patterning the third-rail metal or metal silicide layer and the third-rail heavily doped semiconductor layer of the first conductivity type during the step of patterning to form the plurality of third rails.

13. The method of claim 13, wherein all layers in the second rails are patterned by etching during one etching step.

14. The method of claim 13, further comprising:

forming first vias which extend through the second-rail gate insulating layer and the second-rail lightly doped semiconductor channel layer to the first rails;

depositing the second-rail heavily doped semiconductor layer of the first conductivity type into the first vias such that the second-rail heavily doped semiconductor layer of the first conductivity type contacts the first-rail heavily doped semiconductor layer of the first conductivity type;

forming second vias which extend through the third-rail gate insulating layer and the third-rail lightly doped semiconductor layer to the second rails; and

depositing the third-rail heavily doped semiconductor layer of the second conductivity type into the second vias such that the third-rail heavily doped semiconductor layer of the second conductivity type contacts the second-rail heavily doped semiconductor layer of the second conductivity type.

16. A monolithic three-dimensional array of active devices comprising odd and even levels of field effect transistors, wherein:

odd levels comprise transistors of a first polarity;

even levels comprise transistors of a second polarity;

each transistor comprises a gate electrode, source, and drain, wherein the gate electrodes, sources, and drains of the transistors of at least two levels comprise polysilicon;

current flows between the source and the drain in a first direction through transistors of the first polarity; and

current flows between the source and the drain in a second direction not parallel to the first direction through transistors of the second polarity.

17. The array of claim 17, further comprising:

a substrate;

a plurality of first rails disposed at a first height above the substrate, extending in the first direction, said plurality of first rails comprising sources and drains of the transistors in a first level;

a plurality of second rails in contact with the first rails, at a second height different from the first height, extending in a second direction, said second rails comprising gate electrodes of the transistors in the first level and further comprising sources and drains of the transistors in a second level; and

a plurality of third rails in contact with the second rails, at a third height different from the second height, extending in the first direction, such that the second rails are located between the first rails and the third rails, said third rails comprising gate electrodes of the transistors in the second level.

18. The array of claim 18, wherein the second direction is substantially orthogonal to the first direction.