System and method for transferring data over a communication medium using double-buffering

• US 6,985,977 B2
• Filed: 08/30/2002
• Issued: 01/10/2006
• Est. Priority Date: 08/30/2002
• Status: Expired due to Term

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Vrancic, Aljosa
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Schneider, Joshua D.
• Application Number:
  US10/231,538
• Publication Number:
  US 20040044811A1
• Time in Patent Office: 1,229 Days
• Field of Search: 710/52, 710/53, 710/57, 710/22, 710/23, 710/24, 710/25, 710/305, 710/306, 710/56, 710 58- 61, 711/220, 701/33, 358/115
• US Class Current: 710/59
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Abstract

System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

Claims

1. A method for transferring data in a system including a host computer system coupled to a device, the method comprising:

a first direct memory access (DMA) channel of the device transferring first data from the host computer system into a first buffer of the device;

a second DMA channel of the device transferring the first data from the first buffer;

the first DMA channel of the device transferring second data from the host computer system into a second buffer of the device concurrently with said second DMA channel transferring the first data from the first buffer;

synchronizing the first DMA channel and the second DMA channel, after said first DMA channel transferring second data into the second buffer concurrently with the second DMA channel transferring the first data from the first buffer;

wherein said synchronizing comprises;

the first DMA channel entering a synchronization point;

the first DMA channel issuing a continue command to the second DMA channel, thereby awakening the second DMA channel if the second DMA channel is paused;

the first DMA channel issuing a pause command to itself, thereby pausing itself;

the second DMA channel entering the synchronization point;

the second DMA channel issuing a continue command to the first DMA channel, thereby awakening the first DMA channel;

the second DMA channel issuing a pause command to itself, thereby pausing itself; and

the first DMA channel issuing a continue command to the second DMA channel, thereby awakening the second DMA channel;

wherein, after said first DMA channel issuing the continue command to the second DMA channel, the first DMA channel and the second DMA channel are operable to proceed with further transferring data in a concurrent manner.

2. The method of claim 1, further comprising:

the first DMA channel transferring third data into the first buffer; and

the second DMA channel transferring the second data from the first buffer concurrently with said first DMA channel transferring third data.

3. The method of claim 1,

wherein, after said second DMA channel issuing the continue command to the first DMA channel, the first DMA channel and the second DMA channel are operable to proceed with said transferring data in a synchronous manner.

4. The method of claim 1, further comprising:

after said first DMA channel entering the synchronization point, the first DMA channel issuing a first single atomic command, comprising;

issuing a pause command to the first DMA channel; and

issuing a continue command to the second DMA channel, thereby awakening the second DMA channel if the second DMA channel is paused;

after said second DMA channel entering the synchronization point, the second DMA channel issuing a second single atomic command, comprising;

issuing a pause command to the second DMA channel; and

issuing a continue command the first DMA channel to awaken the first DMA channel, thereby awakening the first DMA channel if the first DMA channel is paused.

5. The method of claim 4,

wherein, during said first DMA channel issuing the first single atomic command, the second DMA channel is excluded from issuing other atomic commands;

and

wherein, during said second DMA channel issuing the second single atomic command, the first DMA channel is excluded from issuing other atomic commands.

6. The method of claim 4,

wherein the first DMA channel does not pause itself if requested until the first single atomic command issued by the first DMA channel is performed;

and

wherein the second DMA channel does not pause itself if requested until the second single atomic command issued by the second DMA channel is performed.

7. The method of claim 6, further comprising:

the first DMA channel issuing a second continue command to the second DMA channel, thereby awakening the second DMA channel if the second DMA channel is paused;

the second DMA channel issuing a second continue command to the first DMA channel, thereby awakening the first DMA channel if the first DMA channel is paused;

wherein, after said first DMA channel issuing the second continue command to the second DMA channel, and said second DMA channel issuing the second continue command to the first DMA channel, the first DMA channel and the second DMA channel are operable to proceed with further transferring data in a concurrent manner.

8. The method of claim 1, further comprising:

the first DMA channel issuing a first single atomic command, comprising;

issuing a continue command to the second DMA channel, thereby awakening the second DMA channel if the second DMA channel is paused; and

issuing a pause command to itself, thereby pausing itself;

wherein, during said first DMA channel issuing the first single atomic command, the second DMA channel is excluded from issuing other atomic commands;

the method further comprising;

the second DMA channel issuing a second single atomic command, comprising;

issuing a continue command to the first DMA channel, thereby awakening the first DMA channel if the first DMA channel is paused; and

issuing a pause command to itself, thereby pausing itself;

wherein, during said second DMA channel issuing the second single atomic command, the first DMA channel is excluded from issuing other atomic commands;

the method further comprising;

the first DMA channel issuing a second continue command to the second DMA channel, thereby awakening the second DMA channel if the second DMA channel is paused;

the second DMA channel issuing a second continue command to the first DMA channel, thereby awakening the first DMA channel if the first DMA channel is paused;

wherein, after said first DMA channel issuing the second continue command to the second DMA channel, and said second DMA channel issuing the second continue command to the first DMA channel, the first DMA channel and the second DMA channel are operable to proceed with further transferring data in a concurrent manner.

9. The method of claim 1, further comprising:

the second DMA channel transferring the second data from the second buffer after completion of said transferring the first data from the first buffer; and

the first DMA channel transferring third data from the host computer system into the first buffer concurrently with said second DMA channel transferring the second data from the second buffer.

10. The method of claim 1,

wherein said first DMA channel transferring the first data from the host computer into the first buffer of the device comprises the first DMA channel transferring first requested data and first pre-fetch data into the first buffer, wherein the first pre-fetch data includes data additional to the first requested data and associated with the first requested data.

11. The method of claim 10,

wherein said first DMA channel transferring the second data from the host computer into the second buffer of the device comprises the first DMA channel transferring second requested data and second pre-fetch data into the second buffer, wherein the second pre-fetch data includes data additional to the second requested data and associated with the second requested data.

12. The method of claim 10, further comprising:

transferring the first requested data from the first buffer to a first temporary memory after transferring the first data into the first buffer, wherein said transferring the first requested data from the first buffer to the first temporary memory location operates to satisfy a first read request.

13. The method of claim 1, further comprising:

the second DMA channel transferring the second data from the second buffer after completion of said transferring the first data from the first buffer;

wherein said second DMA channel of the device transferring the first data from the first buffer comprises transferring the first data from the first buffer to a FIFO memory; and

wherein said transferring the second data from the second buffer comprises transferring the second data from the second buffer to the FIFO memory.

14. The method of claim 1, wherein said second DMA channel of the device transferring the first data from the first buffer is performed after said first DMA channel transferring the first data from the host computer into the first buffer of the device.

15. The method of claim 1, wherein the device is a data acquisition device.

16. The method of claim 1, wherein the device and the host computer system are coupled via a serial bus;

wherein said transferring the first data from the host computer system is performed through the serial bus.

17. The method of claim 16, wherein the serial bus comprises a Universal Serial Bus (USB).

18. The method of claim 16, wherein the serial bus comprises an IEEE 1394 bus.

19. The method of claim 16, wherein the serial bus comprises an Ethernet bus.

20. A method for transferring data in a system including a host computer system coupled through a communication medium to a device, wherein the device comprises a first direct memory access (DMA) channel, a second DMA channel, a first buffer, and a second buffer, wherein the first buffer stores first data, the method comprising:

the second DMA channel of the device transferring the first data from the first buffer of the device;

the first DMA channel reading second data from the host computer system;

the first DMA channel storing the second data in the second buffer;

wherein said second DMA channel of the device transferring the first data from the first buffer and said first DMA channel storing the second data in the second buffer are performed concurrently;

the method further comprising;

synchronizing the first DMA channel and the second DMA channel after said second DMA channel of the device transferring the first data from the first buffer and said first DMA channel storing the second data in the second buffer, wherein said synchronizing comprises;

the first DMA channel entering a synchronization point;

the first DMA channel issuing a pause command, thereby pausing itself;

the second DMA channel entering the synchronization point; and

the second DMA channel issuing a continue command to the first DMA channel, thereby awakening the first DMA channel;

wherein, after said second DMA channel issuing the continue command to the first DMA channel, the first DMA channel and the second DMA channel are operable to proceed transferring data in a concurrent manner.

21. The method of claim 20, further comprising:

determining if there are more data to read and transfer;

if there are no more data to read and transfer, then terminating said reading and said transferring data.

22. The method of claim 20, further comprising:

the first DMA channel reading third data from the host computer system;

the first DMA channel storing the third data in the first buffer; and

the second DMA channel transferring the second data from the second buffer;

wherein said first DMA channel storing the third data in the first buffer and said second DMA channel transferring the second data from the second buffer are performed in a concurrent manner.

23. The method of claim 20, wherein the device is a data acquisition device.

24. The method of claim 20, wherein the communication medium comprises a serial bus.

25. The method of claim 24, wherein the serial bus comprises a Universal Serial Bus (USB).

26. The method of claim 24, wherein the serial bus comprises an IEEE 1394 bus.

27. The method of claim 24, wherein the serial bus comprises an Ethernet bus.

28. A system for transferring data, the system comprising:

a device, comprising;

a first buffer;

a second buffer;

a first direct memory access (DMA) channel; and

a second DMA channel; and

a host computer system coupled to the device via a communication medium;

wherein the first DMA channel is operable to transfer first data from the host computer system into the first buffer;

wherein the second DMA channel is operable to transfer the first data from the first buffer;

wherein the first DMA channel is further operable to transfer second data from the host computer system into the second buffer concurrently with said second DMA channel transferring the first data from the first buffer;

wherein the first DMA channel is further operable to;

enter a synchronization point;

issue a continue command to the second DMA channel, thereby awakening the second DMA channel if the second DMA channel is paused;

issue a pause command to the first DMA channel, thereby pausing the first DMA channel;

wherein the second DMA channel is further operable to;

enter the synchronization point;

issue a continue command to the first DMA channel, thereby awakening the first DMA channel;

issue a pause command to the second DMA channel, thereby pausing the second DMA channel;

wherein the first DMA channel is further operable to;

issue a continue command to the second DMA channel, thereby awakening the second DMA channel;

wherein, after the first DMA channel issues the continue command to the second DMA channel, the first DMA channel and the second DMA channel are operable to proceed with further data transfers in a concurrent manner.

29. The system of claim 28,

wherein the first DMA channel is further operable to:

transfer third data into the first buffer;

wherein the second DMA channel is further operable to;

transfer the second data from the second buffer;

wherein the first DMA channel and the second DMA channel are operable to respectively perform said storing the third data in the first buffer and said transferring the second data from the second buffer in a concurrent manner.

30. The system of claim 29,

wherein the device is operable to:

determine if there are more data to transfer from the host computer system; and

wherein, in transferring third data into the first buffer, the first DMA channel is operable to perform said transferring third data into the first buffer if there are more data to transfer.

31. The system of claim 28,

wherein the second DMA channel is further operable to transfer the second data from the second buffer after completion of said transferring the first data from the first buffer.

32. The system of claim 28, wherein the device is a data acquisition device.

33. The system of claim 28, wherein the communication medium comprises a serial bus.

34. The method of claim 33, wherein the serial bus comprises a Universal Serial Bus (USB).

35. The method of claim 33, wherein the serial bus comprises an IEEE 1394 bus.

36. The method of claim 33, wherein the serial bus comprises an Ethernet bus.