High speed interconnect circuit test method and apparatus
First Claim
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1. A test access port comprising:
- a test clock input;
a test mode select input;
a test data in input;
a test data out output;
a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, and a Shift-DR signal, and having a control bus input;
an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output;
a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the Update-DR signal and the Shift-DR signal, the boundary scan register having a modified Clock-DR input;
a delay circuit connected to the test clock input and having a delayed clock output; and
propagation test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, and the modified Clock-DR input to test the propagation of functional signals received by the boundary scan register.
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Abstract
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.
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Citations
3 Claims
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1. A test access port comprising:
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a test clock input; a test mode select input; a test data in input; a test data out output; a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, and a Shift-DR signal, and having a control bus input; an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output; a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the Update-DR signal and the Shift-DR signal, the boundary scan register having a modified Clock-DR input;
a delay circuit connected to the test clock input and having a delayed clock output; andpropagation test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, and the modified Clock-DR input to test the propagation of functional signals received by the boundary scan register.
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2. A test access port comprising:
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a test clock input; a test mode select input; a test data in input; a test data out output; a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, and a Shift-DR signal, and having a control bus input; an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output and a test signal output; a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the test signal output, the Update-DR signal and the Shift-DR signal, the boundary scan register having a modified Clock-DR input; a delay circuit connected to the test clock input and having a delayed clock output; and decay test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, and the modified Clock-DR input to test the RC time decay of functional signals received by the boundary scan register.
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3. A test access port comprising:
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a test clock input; a test mode select input; a test data in input; a test data out output; a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, and a Shift-DR signal, and having a control bus input; an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output and a test signal output; a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the test signal output, and the Shift-DR signal, the boundary scan register having a modified Clock-DR input, a toggle input a flag input and a modified Update-DR input; a delay circuit connected to the test clock input and having a delayed clock output; and
cycle test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, the modified Clock-DR input, the modified Update-DR input, the toggle input, and the flag input to test toggled functional signals received by the boundary scan register.
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Specification