High speed interconnect circuit test method and apparatus

• US 7,073,111 B2
• Filed: 02/11/2003
• Issued: 07/04/2006
• Est. Priority Date: 06/10/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US10/364,100
• Publication Number:
  US 20030229835A1
• Time in Patent Office: 1,239 Days
• Field of Search: None
• US Class Current: 714/727
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G01R 33/093 using multilayer structures, e.g. giant magnetoresistance sensors thin magnetic films H01F10/00

Abstract

A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Claims

1. A test access port comprising:

a test clock input;

a test mode select input;

a test data in input;

a test data out output;

a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, and a Shift-DR signal, and having a control bus input;

an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output;

a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the Update-DR signal and the Shift-DR signal, the boundary scan register having a modified Clock-DR input;

a delay circuit connected to the test clock input and having a delayed clock output; and

propagation test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, and the modified Clock-DR input to test the propagation of functional signals received by the boundary scan register.

2. A test access port comprising:

a test clock input;

a test mode select input;

a test data in input;

a test data out output;

a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, and a Shift-DR signal, and having a control bus input;

an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output and a test signal output;

a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the test signal output, the Update-DR signal and the Shift-DR signal, the boundary scan register having a modified Clock-DR input;

a delay circuit connected to the test clock input and having a delayed clock output; and

decay test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, and the modified Clock-DR input to test the RC time decay of functional signals received by the boundary scan register.

3. A test access port comprising:

a test clock input;

a test mode select input;

a test data in input;

a test data out output;

a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, and a Shift-DR signal, and having a control bus input;

an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output and a test signal output;

a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the test signal output, and the Shift-DR signal, the boundary scan register having a modified Clock-DR input, a toggle input a flag input and a modified Update-DR input;

a delay circuit connected to the test clock input and having a delayed clock output; and

cycle test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, the modified Clock-DR input, the modified Update-DR input, the toggle input, and the flag input to test toggled functional signals received by the boundary scan register.