Method for effectively embedding various integrated circuits within field programmable gate arrays
First Claim
1. An electronic package having a plurality of pre-formed IC chips encapsulated in stackable layers, the electronic package comprising:
- a field programmable gate array (FPGA) encapsulated in a first stackable layer; and
at least one auxiliary logic component encapsulated in a second stackable layer, wherein the auxiliary logic component is coupled to the FPGA with at least one intercommunicated clock, control and/or data signal between the FPGA and the auxiliary logic component, and wherein the auxiliary logic component has a functionality which is mapped into the FPGA.
8 Assignments
0 Petitions
Accused Products
Abstract
A chip stack includes a field programmable gate array (FPGA) and an auxiliary component coupled to the FPGA with intercommunicated clock, control and/or data signals. The auxiliary component has a functionality mapped into the FPGA. The pin definition of the FPGA is redefined so that the FPGA and the auxiliary component in combination operate as a modified FPGA. A test circuit is programmed into the FPGA to exercise the auxiliary component to test functionality and timing performance at full speed. The functionality of the auxiliary component mapped into the FPGA is parameterized, such as for the data word width for reading and/or writing data words of different lengths into the auxiliary component in both an aligned and nonaligned manner. A memory interface allows multiple auxiliary circuits to be accessed through the FPGA either together to generate a wider data word or serially to achieve a greater memory depth.
-
Citations
35 Claims
-
1. An electronic package having a plurality of pre-formed IC chips encapsulated in stackable layers, the electronic package comprising:
-
a field programmable gate array (FPGA) encapsulated in a first stackable layer; and at least one auxiliary logic component encapsulated in a second stackable layer, wherein the auxiliary logic component is coupled to the FPGA with at least one intercommunicated clock, control and/or data signal between the FPGA and the auxiliary logic component, and wherein the auxiliary logic component has a functionality which is mapped into the FPGA. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. A method of configuring an electronic package having a plurality of pre-formed IC chips encapsulated in stackable layers, the method comprising:
-
intercommunicating a field programmable gate array (FPGA) encapsulated in a first stackable layer and at least one auxiliary logic component encapsulated in a second stackable layer, wherein the auxiliary logic component is coupled to the FPGA through at least one common clock, control and/or data signal between the FPGA and the auxiliary logic component; and mapping a functionality of the auxiliary logic component into the FPGA. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
-
Specification