Method for effectively embedding various integrated circuits within field programmable gate arrays

• US 7,082,591 B2
• Filed: 01/17/2003
• Issued: 07/25/2006
• Est. Priority Date: 01/17/2002
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Irvine Sensors Corp.
• Inventors: Carlson, Randolph S.
• Primary Examiner(s): WHITMORE, STACY
• Application Number:
  US10/346,363
• Publication Number:
  US 20040040005A1
• Time in Patent Office: 1,285 Days
• Field of Search: 716/16, 716/18, 714/733
• US Class Current: 326/38
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A chip stack includes a field programmable gate array (FPGA) and an auxiliary component coupled to the FPGA with intercommunicated clock, control and/or data signals. The auxiliary component has a functionality mapped into the FPGA. The pin definition of the FPGA is redefined so that the FPGA and the auxiliary component in combination operate as a modified FPGA. A test circuit is programmed into the FPGA to exercise the auxiliary component to test functionality and timing performance at full speed. The functionality of the auxiliary component mapped into the FPGA is parameterized, such as for the data word width for reading and/or writing data words of different lengths into the auxiliary component in both an aligned and nonaligned manner. A memory interface allows multiple auxiliary circuits to be accessed through the FPGA either together to generate a wider data word or serially to achieve a greater memory depth.

Claims

1. An electronic package having a plurality of pre-formed IC chips encapsulated in stackable layers, the electronic package comprising:

a field programmable gate array (FPGA) encapsulated in a first stackable layer; and

at least one auxiliary logic component encapsulated in a second stackable layer, wherein the auxiliary logic component is coupled to the FPGA with at least one intercommunicated clock, control and/or data signal between the FPGA and the auxiliary logic component, and wherein the auxiliary logic component has a functionality which is mapped into the FPGA.

2. The electronic package of claim 1 where the auxiliary logic component and the FPGA are interconnected through discrete interconnections with each other.

3. The electronic package of claim 1 where the auxiliary logic component and the FPGA are interconnected through commonly shared connections.

4. The electronic package of claim 1 further comprising a plurality of auxiliary logic components, and where the plurality of auxiliary logic components and the FPGA are interconnected through commonly shared connections.

5. The electronic package of claim 1 further comprising a plurality of FPGAs, and where the plurality of FPGAs and the auxiliary logic component are interconnected through commonly shared connections.

6. The electronic package of claim 1 further comprising a plurality of FPGAs, and a plurality of auxiliary logic components, and where the plurality of FPGAs and the plurality of auxiliary logic components are interconnected through commonly shared connections.

7. The electronic package of claim 1 where the FPGA has a pin definition and where the mapping of the functionality into the FPGA redefines the FPGA pin definition.

8. The electronic package of claim 7 where the FPGA with redefined FPGA pin definition and the auxiliary logic component function in combination as a modified FPGA.

9. The electronic package of claim 1 wherein a test circuit is programmed into the FPGA to exercise the auxiliary logic component.

10. The electronic package of claim 9 wherein the test circuit exercises the auxiliary logic component to test functionality and timing performance.

11. The electronic package of claim 10 wherein the test circuit tests functionality and timing performance at full speed of operation of the auxiliary logic component.

12. The electronic package of claim 1 where the auxiliary logic component is a memory circuit.

13. The electronic package of claim 12 wherein a test circuit is programmed into the FPGA to exercise the memory circuit.

14. The electronic package of claim 13 further comprising a plurality of memory circuits as auxiliary logic components and wherein the test circuit exercises each of the memory circuits to test functionality and timing performance.

15. The electronic package of claim 1 wherein the functionality of the auxiliary logic component mapped into the FPGA is parameterized.

16. The electronic package of claim 15 wherein the parameterized functionality of the auxiliary logic component mapped into the FPGA comprises an arbitrary data word width.

17. The electronic package of claim 16 wherein the parameterized functionality of the auxiliary component mapped into the FPGA comprises reading and/or writing data words of different lengths into the auxiliary component in both an aligned and a nonaligned manner.

18. The electronic package of claim 15 wherein the parameterized functionality of the auxiliary logic component mapped into the FPGA comprises a memory interface that allows multiple auxiliary logic circuits to be accessed through the FPGA either together to generate a wider data word or serially to achieve a greater memory depth.

19. A method of configuring an electronic package having a plurality of pre-formed IC chips encapsulated in stackable layers, the method comprising:

intercommunicating a field programmable gate array (FPGA) encapsulated in a first stackable layer and at least one auxiliary logic component encapsulated in a second stackable layer, wherein the auxiliary logic component is coupled to the FPGA through at least one common clock, control and/or data signal between the FPGA and the auxiliary logic component; and

mapping a functionality of the auxiliary logic component into the FPGA.

20. The method of claim 19 where intercommunicating the field programmable gate array (FPGA) and the at least one auxiliary logic component comprises interconnecting the auxiliary logic component and the FPGA through discreet interconnections with each other.

21. The method of claim 19 where intercommunicating the field programmable gate array (FPGA) and the at least one auxiliary logic component comprises interconnecting the auxiliary logic component and the FPGA through commonly shared connections.

22. The method of claim 19, wherein the electronic package includes a plurality of auxiliary logic components, and where the intercommunicating step comprises interconnecting the plurality of auxiliary logic components and the FPGA through commonly shared connections.

23. The method of claim 19, wherein the electronic package includes a plurality of FPGAs, and where the intercommunicating step comprises interconnecting the plurality of FPGAs and the at least one auxiliary logic component through commonly shared connections.

24. The method of claim 19, wherein the electronic package includes a plurality of FPGAs and a plurality of auxiliary logic components, and where the intercommunicating step comprises interconnecting the plurality of FPGAs and the plurality of auxiliary logic components through commonly shared connections.

25. The method of claim 19 where mapping of the functionality into the FPGA comprises redefining a pin definition of the FPGA.

26. The method of claim 25 further comprising operating the FPGA with redefined FPGA pin definition and the auxiliary logic component in combination as a modified FPGA.

27. The method of claim 19 further comprising programming a test circuit into the FPGA and exercising the auxiliary logic component with the test circuit programmed into the FPGA.

28. The method of claim 27 wherein exercising the auxiliary logic component with the test circuit programmed into the FPGA comprises exercising a memory circuit.

29. The method of claim 28 further comprising exercising a plurality of memory circuits as auxiliary logic components to test functionality and timing performance.

30. The method of claim 27 wherein exercising the auxiliary logic component with the test circuit programmed into the FPGA tests functionality and timing performance of the auxiliary logic component.

31. The method of claim 30 wherein the test circuit tests functionality and timing performance at full speed of operation of the auxiliary logic component.

32. The method of claim 19 wherein mapping the functionality of the auxiliary logic component into the FPGA comprises mapping a parameterized functionality of the auxiliary logic component mapped into the FPGA.

33. The method of claim 32 wherein mapping a parameterized functionality of the auxiliary logic component mapped into the FPGA comprises mapping reading and/or writing an arbitrary data word width into or out of the auxiliary logic component by means of the FPGA.

34. The method of claim 33 wherein mapping reading and/or writing an arbitrary data word width into or out of the auxiliary logic component by means of the FPGA comprises reading and/or writing data words of different lengths into the auxiliary logic component in both an aligned and a nonaligned manner.

35. The method of claim 32 wherein mapping a parameterized functionality of the auxiliary logic component mapped into the FPGA comprises accessing multiple auxiliary logic circuits through a memory interface coupled to the FPGA either to generate a wider data word or serially to achieve a greater memory depth.