Multi-level ONO flash program algorithm for threshold width control
First Claim
1. A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:
- providing one or more unprogrammed multi-level flash memory bits to be programmed;
performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and
performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage; and
generating a dynamic fast-bit drain voltage for each of the program levels on the wordline;
wherein generating the dynamic fast-bit drain voltage comprises;
selecting groups of sample bits from the wordline associated with each program level;
selecting a starting drain voltage for each program level from the lowest allowable drain voltage for each program level;
applying program pulses to a first group of sample bits associated with a first program level;
increasing one of the drain voltage, a gate voltage, and a combination of the drain and gate voltages of the first group of sample bits;
determining a first drain voltage at which a fast-bit of the group of sample bits is programmed or a maximum drain voltage level is attained; and
reselecting another group of sample bits associated with a program level, applying program pulses, increasing one of the drain and gate voltages until a fast-bit drain voltage is determined for each group of sample bits associated with a respective program level.
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Abstract
Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.
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Citations
53 Claims
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1. A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:
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providing one or more unprogrammed multi-level flash memory bits to be programmed; performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage; and generating a dynamic fast-bit drain voltage for each of the program levels on the wordline;
wherein generating the dynamic fast-bit drain voltage comprises;selecting groups of sample bits from the wordline associated with each program level; selecting a starting drain voltage for each program level from the lowest allowable drain voltage for each program level; applying program pulses to a first group of sample bits associated with a first program level; increasing one of the drain voltage, a gate voltage, and a combination of the drain and gate voltages of the first group of sample bits; determining a first drain voltage at which a fast-bit of the group of sample bits is programmed or a maximum drain voltage level is attained; and reselecting another group of sample bits associated with a program level, applying program pulses, increasing one of the drain and gate voltages until a fast-bit drain voltage is determined for each group of sample bits associated with a respective program level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:
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providing one or more unprogrammed multi-level flash memory bits to be programmed; performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage, wherein the rough programming operation comprises; setting a program verify value to correspond to the rough threshold voltage; selecting a predetermined programming profile of drain and gate voltages for programming the bits based on a program pattern of the cell bit-pairs; applying a programming pulse to the bits according to the programming profile; reapplying programming pulses to the bits according to the programming profile until the threshold voltage of each bit of the memory cells generally corresponds to the rough threshold voltage of the program verify value; and deselecting the rough programmed bits.
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13. A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:
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providing one or more unprogrammed multi-level flash memory bits to be programmed; performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage, wherein the rough and fine programming operations comprise programming pulses of drain and gate voltages applied to the memory bits, and wherein the programming pulses of the rough and fine programming operations have about the same pulse width and about the same step amplitude.
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14. A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:
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providing one or more unprogrammed multi-level flash memory bits to be programmed; performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage, wherein the fine programming operation comprises; setting a program verify value to correspond to the target threshold voltage; selecting a predetermined programming profile of drain and gate voltages for programming the bits based on a program pattern of the cell bit-pairs; applying a programming pulse to the bits according to the programming profile; reapplying programming pulses to the bits according to the programming profile until the threshold voltage of each bit of the memory cells generally corresponds to the fine threshold voltage of the program verify value; and deselecting the fine programmed bits. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:
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providing one or more unprogrammed multi-level flash memory bits to be programmed; performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage, further comprising selecting all of the bits on the wordline that are to have the bit-pairs programmed to the same program pattern.
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22. A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:
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providing one or more unprogrammed multi-level flash memory bits to be programmed; performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage, wherein all the cell bit-pairs selected on the wordline have the same program patterns, and wherein the predetermined programming profile comprises a predetermined pattern of the drain and gate voltages that are applied to the memory bits over successive programming pulses based on the program pattern of the cell bit-pairs selected. - View Dependent Claims (23, 24, 25)
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26. A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:
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providing one or more unprogrammed multi-level flash memory bits to be programmed; performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and
p1 performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage, wherein the rough threshold voltage is offset lower than the target threshold voltage by about 150–
450 mV.
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27. A method of programming one or more bits of memory cell bit-pairs on a wordline of a multi-level flash memory array, the bits of the memory cells having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:
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providing one or more unprogrammed multi-level flash memory bits selected to be programmed to the same program pattern; generating a dynamic fast-bit drain voltage for each of the program levels on the wordline; performing a rough programming operation on the bits of the array based on one of the fast-bit drain voltages and the cell program pattern until the threshold voltage of each bit of the memory cells generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and performing a fine programming operation on the memory bits of the array until the threshold voltage of each bit generally corresponds to the target threshold voltage. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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Specification