Reconfigurable digital processing system for space

• US 7,142,953 B2
• Filed: 09/25/2003
• Issued: 11/28/2006
• Est. Priority Date: 01/11/2002
• Status: Active Grant

• Current Assignee: Gula Consulting Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Dennis, Charles A., Marshall, Joseph R., Santee, Steven G., Dennis, Alan F.
• Primary Examiner(s): ARTHUR JEANGLAUDE, GERTRUDE
• Application Number:
  US10/672,844
• Publication Number:
  US 20040148069A1
• Time in Patent Office: 1,160 Days
• Field of Search: 701/9, 701/13, 701/29, 701/33, 701/43, 700/18, 700/87, 712/1
• US Class Current: 701/13
• CPC Class Codes: G06F 11/142 Reconfiguring to eliminate the error group management mechanisms in a peer-to-peer network H04L67/1044
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor. In one embodiment, multiple FPGAs are connected together by a data bus and are also provided with data pipes which interconnect selected FPGAs together to provide the necessary processing function. Flexibility in reconfiguration includes the utilizing of a timing and synchronization block as well as a common configuration block which when coupled to an interconnect block permits reconfiguration of a customizable application core, depending on the particular signal processing function desired. The result is that damaged or inoperable signal processing components can be repaired in space without having to physically attend to the hardware by transmitting to the spacecraft commands which reconfigure the particular FPGAs thus to alter their signal processing function. Also mission changes can be accomplished by reprogramming the FPGAs.

Claims

1. A reconfigurable digital processing system for use in space to permit remote reconfiguration of a space vehicle-born processor, comprising:

a field programmable gate array functioning as a signal processor for performing a signal processing task aboard said space vehicle;

a receiver on said space vehicle for reviewing uploaded commands for reconfiguring said field programmable gate array; and

,

a field programmable gate array configuring unit coupled to said receiver for reconfiguring said field programmable gate array responsive to said uploaded commands, whereby a field programmable gate array aboard said space vehicle can be reconfigured from a remote location.

2. The reconfigurable digital processing system of claim 1, wherein said field programmable gate array includes a testing unit for ascertaining if the operation of said field programmable gate array matches that of a prior configuration, and further including a reconfiguration unit for restoring the priorly configured operation of said field programmable gate array responsive to an output of said testing unit indicating a repairable malfunction of said field programmable gate array.

3. The reconfigurable digital processing system of claim 1, and further including a number of field programmable gate arrays and a shadowing for providing inputs to each of said gate arrays to permit parallel processing by said field programmable gate arrays.

4. The reconfigurable digital processing syscem of claim 1, wherein said field programmable gate array includes a bus and at least one data pipe coupled thereto.

5. The reconfigurable digital processing system of claim 4, wherein said bus and said data pipe includes a clock coupled thereto.

6. The reconfigurable digital processing system of claim 1, wherein said field programmable gate array includes a customizable core, an interconnect block coupled to said core, a timing and synchronization unit connected to said interconnect block, an external I/O block coupled to said timing and synchronization unit, the coupling of said interconnect block and said core including at least one data pipe, the coupling of said external I/O block and said timing and synchronization unit including at least one data pipe.

7. The reconfigurable digital processing system of claim 6, wherein said field programmable gate array includes a common configuration and status unit coupled to said external I/O block and to said core to provide internal interface control thereof.

8. The reconfiguration digital processing system of claim 7, and further including control logic for providing a time stamp to said configuration and status common configuration and status unit.

9. The reconfigurable digital processing system of claim 8, and further including at least one bus coupled between said core and said external I/O block, said control logic coupled to said external I/O block for control of the timing of the signals on said bus.

10. The reconfigurable digital processing of claim 9, and further including a shadow bus control unit coupled between said external I/O block and said common infrastructure configuration and status unit for the control of shadow functions.

11. A reconfigurable digital processing system, comprising:

a card having a number of field programmable gate arrays thereon;

a control unit for controlling the configuration of said field programmable gate arrays;

a configuration bus coupled between said control unit and said field programmable gate arrays;

a bus interface coupled to said field programmable gate arrays; and

,

a shadow interconnect between said field programmable gate arrays for connecting said arrays together to perform parallel processing tasks.

12. The systom of claim 11, and further including SRAM storage for said control unit and EEPROM storage for memory and address data from said bus interface.