Method and apparatus for adjusting the performance of a synchronous memory system
First Claim
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1. A dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:
- a receiver to sample an externally provided value that is representative of a supply voltage being provided to the memory device;
a programmable register, coupled to the receiver, to store the value; and
a register to store data transfer rate information, wherein an internal circuit is adjusted based on the data transfer rate information and the value stored in the programmable register.
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Abstract
A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.
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Citations
28 Claims
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1. A dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:
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a receiver to sample an externally provided value that is representative of a supply voltage being provided to the memory device; a programmable register, coupled to the receiver, to store the value; and a register to store data transfer rate information, wherein an internal circuit is adjusted based on the data transfer rate information and the value stored in the programmable register.
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2. A dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:
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a receiver to sample an externally provided value that is representative of a supply voltage being provided to the memory device; and a programmable register, coupled to the receiver, to store the value; and a clock synchronization circuit to receive an external clock signal and synchronize outputting of data from the memory device with the external clock signal. - View Dependent Claims (3, 4, 5)
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6. A dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:
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receiver means for sampling an externally provided value that is representative of a supply voltage being provided to the memory device; a programmable means, coupled to the receiver means, for storing the value; and means for storing data transfer rate information, wherein an internal circuit is adjusted based on the data transfer rate information and the value stored in the programmable means.
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7. A dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:
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receiver means for sampling an externally provided value that is representative of a supply voltage being provided to the memory device; a programmable means, coupled to the receiver means, for storing the value; and clock synchronization means to receive an external clock signal and synchronize outputting of data from the memory device with the external clock signal, wherein the clock synchronization means is adjusted based on the value stored in the programmable means. - View Dependent Claims (8)
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9. A method of controlling a dynamic random access memory device by a memory controller, wherein the method comprises:
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in the memory controller, accessing information indicative of a supply voltage potential; and providing the information to the memory device, the memory device to process the information such that a clock alignment circuitry in the memory device is adjusted based on the supply voltage potential. - View Dependent Claims (10, 11, 12, 13)
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14. A method of operation in a memory device that includes a plurality of memory cells, the method comprising:
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receiving a value which is representative of a supply voltage potential being provided to the memory device; and adjusting a clock alignment circuit based on the value, the clock alignment circuit to synchronize transmission of data from the memory device. - View Dependent Claims (15, 16, 17, 18, 19, 21, 22, 23, 24)
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20. The method of 14 wherein the clock alignment circuit is a phase lock loop circuit, wherein the phase lock loop circuit generates an internal clock signal having a predetermined timing relationship with an external clock signal to synchronize the transmission of the data from the memory device.
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25. A synchronous integrated circuit memory device having an array of dynamic memory cells, wherein the memory device comprises:
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a plurality of receivers to receive an externally provided value that is representative of a supply voltage potential; and a locked loop circuit, coupled to a plurality of transmitters, to synchronize transmission of data from the memory device with an external clock signal, wherein the locked loop circuit is adjusted using the value. - View Dependent Claims (26, 27, 28)
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Specification