Method and apparatus for adjusting the performance of a synchronous memory system

• US 7,149,856 B2
• Filed: 03/10/2003
• Issued: 12/12/2006
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Donnelly, Kevin S., Barth, Richard M., Tsern, Ely K., Sidiropoulos, Stefanos, Stark, Donald C., Portmann, Clemenz, Davis, Paul G., Chau, Pak Shing, Garlepp, Bruno Werner
• Primary Examiner(s): ELLIS, KEVIN L
• Application Number:
  US10/386,210
• Publication Number:
  US 20040168036A1
• Time in Patent Office: 1,373 Days
• Field of Search: 711/104, 711/105, 711/154, 711/156, 711/167, 711/170, 710/8
• US Class Current: 711/156
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.

Claims

1. A dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:

a receiver to sample an externally provided value that is representative of a supply voltage being provided to the memory device;

a programmable register, coupled to the receiver, to store the value; and

a register to store data transfer rate information, wherein an internal circuit is adjusted based on the data transfer rate information and the value stored in the programmable register.

2. A dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:

a receiver to sample an externally provided value that is representative of a supply voltage being provided to the memory device; and

a programmable register, coupled to the receiver, to store the value; and

a clock synchronization circuit to receive an external clock signal and synchronize outputting of data from the memory device with the external clock signal.

3. The memory device of claim 2 wherein the clock synchronization circuit includes one of a delay locked loop circuit and a phase locked loop circuit.

4. The memory device of claim 2 wherein the clock synchronization circuit includes:

a phase detector to generate information representative of a difference in phase between the external clock signal and the internal clock signal; and

a delay circuit to generate the internal clock signal, wherein an amount of delay of the internal clock signal is varied based on the information representative of the difference in phase between the external clock signal and the internal clock signal.

5. The memory device of claim 2 wherein the programmable register is coupled to the clock synchronization circuit and wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register.

6. A dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:

receiver means for sampling an externally provided value that is representative of a supply voltage being provided to the memory device;

a programmable means, coupled to the receiver means, for storing the value; and

means for storing data transfer rate information, wherein an internal circuit is adjusted based on the data transfer rate information and the value stored in the programmable means.

7. A dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:

receiver means for sampling an externally provided value that is representative of a supply voltage being provided to the memory device;

a programmable means, coupled to the receiver means, for storing the value; and

clock synchronization means to receive an external clock signal and synchronize outputting of data from the memory device with the external clock signal, wherein the clock synchronization means is adjusted based on the value stored in the programmable means.

8. The memory device of claim 7 wherein the clock synchronization means includes:

a phase detector to generate information representative of a difference in phase between the external clock signal and an internal clock signal; and

a delay circuit to generate the internal clock signal, wherein an amount of delay of the internal clock signal is varied based on the information representative of the difference in phase between the external clock signal and the internal clock signal.

9. A method of controlling a dynamic random access memory device by a memory controller, wherein the method comprises:

in the memory controller, accessing information indicative of a supply voltage potential; and

providing the information to the memory device, the memory device to process the information such that a clock alignment circuitry in the memory device is adjusted based on the supply voltage potential.

10. The method of claim 9 wherein the information is provided to the memory device during initialization of the memory device.

11. The method of claim 9 further including providing information indicative of a data transfer rate to the memory device.

12. The method of claim 9 further including providing information indicative of a range of data transfer rates to the memory device.

13. The method of claim 9 wherein accessing the information includes detecting the supply voltage.

14. A method of operation in a memory device that includes a plurality of memory cells, the method comprising:

receiving a value which is representative of a supply voltage potential being provided to the memory device; and

adjusting a clock alignment circuit based on the value, the clock alignment circuit to synchronize transmission of data from the memory device.

15. The method of claim 14 wherein the value is issued to the memory device during an initialization period.

16. The method of claim 14 wherein the clock alignment circuit synchronizes transmission of data such that the data is transmitted synchronously with respect to a clock signal.

17. The method of claim 14 further including decoding the value to generate an internal control signal, wherein the clock alignment circuit is adjusted in response to the internal control signal.

18. The method of claim 14 wherein adjusting the clock alignment circuit includes adjusting a phase mixer in accordance with the value.

19. The method of claim 14 wherein the clock alignment circuit is a delay lock loop circuit, wherein the delay lock loop circuit generates an internal clock signal having a predetermined timing relationship with an external clock signal to synchronize the transmission of the data from the memory device.

21. The method of claim 14 further including adjusting a locking frequency range of the clock alignment circuit, wherein the locking frequency range is adjusted based on the value.

22. The method of claim 14 further including generating an internal clock signal using the clock alignment circuit, the internal clock signal having a predetermined phase relationship with an external clock signal, wherein the internal clock signal synchronizes the transmission of the data from the memory device.

23. The method of claim 22 further including:

detecting a phase differential between the external clock signal and the internal clock signal;

generating the internal clock signal using a delay element; and

varying an amount of delay in the delay element to adjust the phase differential between the internal clock signal and the external clock signal.

24. The method of claim 14 further including:

receiving information which is representative of a data transfer rate; and

storing the information which is representative of a data transfer rate in a register disposed within the memory device.

20. The method of 14 wherein the clock alignment circuit is a phase lock loop circuit, wherein the phase lock loop circuit generates an internal clock signal having a predetermined timing relationship with an external clock signal to synchronize the transmission of the data from the memory device.

25. A synchronous integrated circuit memory device having an array of dynamic memory cells, wherein the memory device comprises:

a plurality of receivers to receive an externally provided value that is representative of a supply voltage potential; and

a locked loop circuit, coupled to a plurality of transmitters, to synchronize transmission of data from the memory device with an external clock signal, wherein the locked loop circuit is adjusted using the value.

26. The integrated circuit memory device of claim 25 wherein the locked loop circuit further includes a mixer circuit to vary a phase range of an internal clock signal in accordance with the value, wherein the locked loop circuit synchronizes the transmission of data from the memory device with the external clock signal using the internal clock signal.

27. The integrated circuit memory device of claim 25 further including:

a programmable register to store the value; and

decoder circuitry coupled to the programmable register to decode the value stored within the programmable register.

28. The integrated circuit memory device of claim 27 further including a register to store data transfer rate information, wherein the locked loop circuit is adjusted in accordance with the value stored in the programmable register and the data transfer rate information.