Placement tool for wafer scale caps

• US 7,173,332 B2
• Filed: 12/08/2003
• Issued: 02/06/2007
• Est. Priority Date: 01/10/2001
• Status: Expired due to Fees

• Current Assignee: Kerwar Acquisitions LLC (Intellectual Ventures LLC)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Mitchell, James M.
• Application Number:
  US10/728,985
• Publication Number:
  US 20040121517A1
• Time in Patent Office: 1,156 Days
• Field of Search: 257/620, 257/666
• US Class Current: 257/709
• CPC Class Codes: B29C 2035/0822 using IR radiation
• CPC Class Codes: B29C 2043/503 using ejector pins, rods
• CPC Class Codes: B29C 33/0022 Multi-cavity moulds B29C33/301 takes precedence
• CPC Class Codes: B29C 33/3842 Manufacturing moulds, e.g. shaping the mould surface by machining
• CPC Class Codes: B29C 43/36 Moulds for making articles of definite length, i.e. discrete articles
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0127 Using a carrier for applying a plurality of packaging lids to the system wafer
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: Y10S 257/924 with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Abstract

A tool is used to hold an array of wafer scale protective caps and place the array onto a semiconductor wafer. The tool comprises a first tool half made from a semiconductor which has a coefficient of thermal expansion which is about the same as that of the wafer. The first tool half has surface features for molding and retaining the array. The caps have central areas surrounded by sidewalls.

Claims

1. A tool used to hold an array of wafer scale protective caps and place the array onto a semiconductor wafer, the tool comprising:

a first tool half made from a semiconductor that has a coefficient of thermal expansion which is about the same as that of the wafer, the first tool half having surface features which have a converse shape to a part of a shape of the caps, the surface features being configured to mold the caps to have said part of said shape; and

a second tool half having an upper surface in which grooves are formed, the surface features of the first tool half and the grooves cooperating so as to define mold cavities for the caps.

wherein the converse shape of the surface features is configured to retain the array of molded caps for placement onto the wafer.

2. The tool of claim 1, wherein the first tool half is made from silicon.

3. The tool of claim 1, wherein the first tool half and the second half together mold for the array.

4. The tool of claim 1, wherein the surface features of the first tool half have a spacing which corresponds to a spacing of the wafer.

5. The tool of claim 1, wherein the surface features are formed using cryogenic deep silicon etching techniques.

6. The tool of claim 1, wherein:

the first tool half has a lower surface in which the surface features are arranged as recessed;

the second tool half has an upper surface in which surface features having a converse shape to a remaining part of the shape of the caps are arranged, the surface features being configured to mold the caps to have said remaining part of said shape.

7. The tool of claim 1, wherein:

the first tool half includes first eject holes formed through it;

the holes located in registry with the surface features;

there being provided a first half release wafer from which projects a number of pins;

the pins located in registry with the first holes;

the first tool half having a thickness in the area of the first holes, the pins being longer than the thickness.

8. The tool of claim 7, wherein:

the first half release wafer has a first position in which the pins are flush with an interior end of the first holes;

there being a gap between the first tool half and the first half release wafer when the first half release wafer is in the first position.

9. The tool of claim 7, wherein:

the second tool half includes second holes formed through it;

there being provided a second half release wafer from which projects a number of pins;

the pins located in registry with the second holes;

the second tool half having a thickness in the area of the second holes, the pins being longer than the thickness.

10. The tool of claim 9, wherein:

the second half release wafer has a first position in which the pins are flush with an interior end of the second holes;

there being a second gap between the second tool half and the second half release wafer when the second half release wafer is in the first position.

11. The tool of claim 10, wherein:

the second holes are located in registry with grooves fanned in an upper surface of the second tool half, the grooves being cap molding features.

12. The tool of claim 1, wherein the first tool half is comprised of a semiconductor that is transparent to infrared light of a wavelength of about 1000–

5000 nm.

13. The tool of claim 12, wherein the second tool half is comprised of a semiconductor that is transparent to infrared light of a wavelength of about 1000–

5000 nm.

14. The tool of claim 1, wherein:

the first tool half includes first holes formed through it;

the holes located in registry with the surface features;

there being provided a first half release wafer from which projects a number of pins;

the pins located in registry with the first holes;

the first tool half having a thickness in the area of the first holes, the pins being longer than the thickness;

the first half release wafer having a first position in which the pins are flush with an interior end of the first holes;

there being a gap between the first tool half and the first half release wafer when the first half release wafer is in the first position; and

the second tool half includes second holes formed through it;

there being provided a second half release wafer from which projects a number of pins;

the pins located in registry with the second holes;

the second tool half having a thickness in the area of the second holes, the pins being longer than the thickness;

the second half release wafer having a first position in which the pins are flush with an interior end of the second holes;

there being a second gap between the second tool half and the second half release wafer when the second half release wafer is in the first position.

15. The tool of claim 14, wherein the first and second tool halves and the first and second half release wafers are comprised of a semiconductor that is transparent to infrared light of a wavelength of about 1000–

5000 nm.

16. The tool of claim 1, wherein:

the first tool half has first portions which separate adjacent surface features;

the second tool half has cooperating and opposite second portions;

the first and second portions corning together when the halves are brought together such that material is squeezed out from between the first and second portions, separating adjacent caps.

17. The tool of claim 1, wherein:

the first tool half has first portions which separate adjacent surface features;

the second tool half has cooperating and opposite second portions;

the first and second portions coming together when the halves are brought together such that material is left as a thin layer between the first and second portions, the caps thus being fanned as an array joined by the thin layer.

18. The tool of claim 1, wherein surface features are formed by electron beam or X-ray lithography.