Signal processing circuit, image sensor IC, and signal processing method

• US 7,189,953 B2
• Filed: 02/23/2004
• Issued: 03/13/2007
• Est. Priority Date: 02/26/2003
• Status: Expired due to Term

• Current Assignee: Ablic Inc. (Minebea Mitsumi, Inc.)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Machida, Satoshi
• Primary Examiner(s): Epps; Georgia
• Assistant Examiner(s): WYATT, KEVIN S
• Application Number:
  US10/784,494
• Publication Number:
  US 20040195491A1
• Time in Patent Office: 1,114 Days
• Field of Search: 250/208.1, 348/241, 348/272, 348/301, 348/302, 348/303
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/672 between adjacent sensors or output registers for reading a single image
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A signal processing circuit has a sample/hold circuit for sampling an input signal comprised of a first signal and a second signal and for holding the first signal. The first signal comprises an optical signal obtained due to storage of electric charges generated due to light incident upon a photoelectric converter, and the second signal comprises a reference signal obtained due to resetting of the photoelectric converter. A subtracter receives an output signal of the sample/hold circuit and the input signal and obtains a difference between the output signal of the sample/hold circuit and the input signal. A voltage clamp circuit clamps a part or all of an output signal from the subtracter.

Claims

1. A signal processing circuit comprising:

a sample/hold circuit that samples an input signal comprised of a first signal and a second signal and for holding the first signal, the first signal comprising an optical signal obtained due to storage of electric charges generated due to light incident upon a photoelectric converter, and the second signal comprising a reference signal obtained due to resetting of the photoelectric converter;

a subtracter connected to receive an output signal of the sample/hold circuit and the input signal and for obtaining a difference between the output signal of the sample/hold circuit and the input signal; and

a voltage clamp circuit for clamping a part or all of an output signal from the subtracter.

2. A signal processing circuit according to claim 1;

wherein the sample/hold circuit comprises a first sample/hold circuit; and

further comprising a second sample/hold circuit connected to an output of the voltage clamp circuit for sampling an output signal of the voltage clamp circuit when the first sample/hold circuit holds the first signal.

3. A signal processing circuit according to claim 1;

wherein the subtracter is a differential amplifier comprised of an operational amplifier and a plurality of resistors; and

wherein a reference voltage of the differential amplifier and a clamping voltage of the voltage clamp circuit are common to each other.

4. An image sensor IC comprising:

a signal processing circuit as claimed in claim 1 formed together with the photoelectric converter on one semiconductor substrate.

5. An image sensor comprising:

a plurality of image sensor ICs as claimed in claim 4.

6. An image sensor IC comprising:

a photoelectric converter;

a signal processing circuit connected to an output terminal of the photoelectric converter, the signal processing circuit comprising a sample/hold circuit for sampling an input signal comprised of an optical signal and a reference signal and for holding the optical signal, a subtracter connected to receive the output signal of the sample/hold circuit and the input signal and for obtaining a difference between the output signal of the sample/hold circuit and the input signal, and a voltage clamp circuit for clamping an output signal of the subtracter, the optical signal being obtained due to storage of electric charges generated due to light incident upon the photoelectric converter, and the second signal comprising a reference signal obtained due to resetting of the photoelectric converter;

a signal output terminal connected to an output terminal of the signal processing circuit;

a reference voltage terminal connected to a terminal at which a reference voltage for the signal processing circuit appears;

a reference voltage circuit; and

a resistor disposed between the reference voltage circuit and the reference voltage.

7. A close contact type image sensor comprising:

a plurality of image sensor ICs according to claim 6, the reference voltage terminals of the respective image sensor ICs being electrically connected to one another.

8. An image sensor IC according to claim 6;

further comprising a gain amplifier for amplifying the output signal clamped by the voltage clamp circuit, a reference voltage for the gain amplifier being supplied through the reference voltage terminal.

9. A signal processing method, comprising the steps of:

generating an input signal comprised of an optical signal component obtained due to storage of electric charges generated due to light incident upon a photoelectric converter and a reference signal component obtained due to resetting of the photoelectric converter;

sampling the input signal and holding the optical signal component of the input signal using a sample/hold circuit;

obtaining a difference between an output signal of the sample/hold circuit and the input signal using a subtracter; and

clamping a part or all of an output signal from the subtracter using a voltage clamp circuit.

10. A signal processing method according to claim 9;

further comprising the steps of amplifying the input signal and an output signal from the sample/hold circuit, and inputting the amplified input and output signals to the subtracter.

11. A signal processing method according to claim 9;

wherein the sample/hold circuit comprises a first sample/hold circuit; and

further comprising the step of sampling an output signal from the voltage clamp circuit using a second sample/hold circuit when the first sample/hold circuit holds the optical signal component.