Integrated circuit employable with a power converter

• US 7,190,026 B2
• Filed: 08/23/2004
• Issued: 03/13/2007
• Est. Priority Date: 08/23/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Enpirion, Inc. (MediaTek, Inc.)
• Inventors: Lotfi, Ashraf W., Tan, Jian
• Primary Examiner(s): Nguyen; Tuan T.
• Assistant Examiner(s): Bernstein; Allison
• Application Number:
  US10/924,091
• Publication Number:
  US 20060039224A1
• Time in Patent Office: 932 Days
• Field of Search: 257/336, 257/338, 257/343
• US Class Current: 257/336
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

An integrated circuit employable with a power converter. In one embodiment, the integrated circuit includes a power switch of a power train of the power converter formed on a semiconductor substrate. The integrated circuit also includes a driver switch of a driver configured to provide a drive signal to the power switch and embodied in a transistor including a gate located over a channel region recessed into the semiconductor substrate. The transistor also includes a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor further includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Claims

1. An integrated circuit employable with a power converter, comprising:

a power switch of a power train of said power converter formed on a semiconductor substrate; and

a driver switch of a driver configured to provide a drive signal to said power switch and embodied in a transistor, including;

a gate located over a channel region recessed into said semiconductor substrate,

a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region,

an oppositely doped well located under and within said channel region, and

a doped region, located between said heavily doped region and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region.

2. The integrated circuit as recited in claim 1 wherein said power switch is a transistor, including:

a gate located over a channel region recessed into said semiconductor substrate,

a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region, and

an oppositely doped well located under and within said channel region.

3. The integrated circuit as recited in claim 2 wherein said transistor employable as said power switch further includes a doped region, located between said heavily doped region and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region thereof.

4. The integrated circuit as recited in claim 1 wherein said transistor, further includes:

another source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region, and

another doped region, located between said heavily doped region of said another source/drain and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region of said another source/drain.

5. The integrated circuit as recited in claim 1 wherein said transistor further includes a gate dielectric layer underlying said gate and gate sidewall spacers about said gate, said transistor further including metal contacts formed over a salicide layer on said gate and said source/drain.

6. The integrated circuit as recited in claim 1 wherein an oppositely doped buried layer is located under said doped region.

7. The integrated circuit as recited in claim 1 further comprising a complementary metal oxide semiconductor device, formed on said semiconductor substrate, that includes a source/drain having a heavily doped region with a doping concentration profile different from said doping concentration profile of said heavily doped region of said source/drain of said transistor.

8. The integrated circuit as recited in claim 1 further comprising a complementary metal oxide semiconductor device employable in a controller of said power converter.

9. The integrated circuit as recited in claim 1 further comprising a switch in a controller of said power converter formed by a transistor, including:

a gate located over a channel region recessed into said semiconductor substrate,

a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region, and

an oppositely doped well located under and within said channel region.

10. The integrated circuit as recited in claim 1 further comprising a micromagnetic device.

11. The integrated circuit as recited in claim 1 further comprising an output filter at an output of said power converter.

12. The integrated circuit as recited in claim 1 further comprising a capacitor associated with a controller of said power converter.

13. The integrated circuit as recited in claim 1 further comprising a linear regulator within a controller of said power converter.

14. The integrated circuit as recited in claim 1 further comprising a soft start circuit within a controller of said power converter.

15. The integrated circuit as recited in claim 1 further comprising protection circuits within a controller of said power converter.

16. An integrated circuit employable with a power converter, comprising:

a power switch of a power train of said power converter formed on a semiconductor substrate;

a complementary metal oxide semiconductor device employable in a controller configured to provide a signal to control a duty cycle of said power switch and formed on said semiconductor substrate; and

a driver switch of a driver configured to provide a drive signal to said power switch as a function of said signal from said controller and embodied in a laterally diffused metal oxide semiconductor device, including;

a gate located over a channel region recessed into said semiconductor substrate,

a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region,

an oppositely doped well located under and within said channel region, and

a doped region, located between said heavily doped region and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region.

17. The integrated circuit as recited in claim 16 wherein said power switch is referenced to a voltage level different from said driver switch and said power switch is a transistor, including:

a gate located over a channel region recessed into said semiconductor substrate,

a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region, and

an oppositely doped well located under and within said channel region.

18. The integrated circuit as recited in claim 17 wherein said transistor employable as said power switch further includes a doped region, located between said heavily doped region and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region thereof.

19. The integrated circuit as recited in claim 16 wherein said laterally diffused metal oxide semiconductor device, further includes:

another source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region, and

another doped region, located between said heavily doped region of said another source/drain and said oppositely doped well, having a doping concentration profile less than a doping concentration profile of said heavily doped region of said another source/drain.

20. The integrated circuit as recited in claim 16 wherein said laterally diffused metal oxide semiconductor device further includes a gate dielectric layer underlying said gate and gate sidewall spacers about said gate, said laterally diffused metal oxide semiconductor device further including metal contacts formed over a salicide layer on said gate and said source/drain.

21. The integrated circuit as recited in claim 16 wherein an oppositely doped buried layer is located under said doped region.

22. The integrated circuit as recited in claim 16 wherein said complementary metal oxide semiconductor device includes a source/drain having a heavily doped region with a doping concentration profile different from said doping concentration profile of said heavily doped region of said source/drain of said laterally diffused metal oxide semiconductor device.

23. The integrated circuit as recited in claim 16 wherein said controller further includes a laterally diffused metal oxide semiconductor device, including:

a gate located over a channel region recessed into said semiconductor substrate,

a source/drain including a lightly doped region located adjacent said channel region and a heavily doped region located adjacent said lightly doped region, and

an oppositely doped well located under and within said channel region.

24. The integrated circuit as recited in claim 16 further comprising a micromagnetic device.

25. The integrated circuit as recited in claim 16 further comprising a shallow trench isolation region formed within said semiconductor substrate and proximate said doped region.

26. The integrated circuit as recited in claim 16 further comprising an output filter at an output of said power converter.

27. The integrated circuit as recited in claim 16 further comprising a capacitor associated with said controller of said power converter.

28. The integrated circuit as recited in claim 16 wherein said controller further includes a linear regulator.

29. The integrated circuit as recited in claim 16 wherein said controller further includes a soft start circuit.

30. The integrated circuit as recited in claim 16 wherein said controller further includes protection circuits.