Single poly non-volatile memory
First Claim
1. An erasable programmable non-volatile memory cell, comprising:
- a first select transistor including a select gate, source/drain, and a first channel region formed between its source and drain, wherein a source line is electrically connected to its source;
a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a second channel region formed between its drain and source, and a floating gate overlying the second channel region;
a second select transistor including the said select gate, source/drain, and a third channel region formed between its source and drain, wherein the source of the second select transistor is coupled to the source line; and
a second floating gate transistor having a drain, a source coupled to the drain of the is second select transistor, a fourth channel region formed between its drain and source, and said floating gate overlying the fourth channel region.
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Accused Products
Abstract
An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a first floating gate channel region formed between its drain and source, and a common floating gate overlying the floating gate channel region; a second select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; and a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a second floating gate channel region formed between its drain and source, and the common floating gate overlying the second floating gate channel region.
45 Citations
19 Claims
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1. An erasable programmable non-volatile memory cell, comprising:
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a first select transistor including a select gate, source/drain, and a first channel region formed between its source and drain, wherein a source line is electrically connected to its source; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a second channel region formed between its drain and source, and a floating gate overlying the second channel region; a second select transistor including the said select gate, source/drain, and a third channel region formed between its source and drain, wherein the source of the second select transistor is coupled to the source line; and a second floating gate transistor having a drain, a source coupled to the drain of the is second select transistor, a fourth channel region formed between its drain and source, and said floating gate overlying the fourth channel region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A non-volatile memory cell comprising a first transistor and a second transistor sharing one floating gate strip, wherein source/drain of the first and second transistors are connected out to independent four terminals, and wherein when programming the non-volatile memory cell, drain of the first transistor is biased to VPP, source of the first transistor is biased to VSS1, drain of the second transistor is floated, and source of the second transistor is biased to VSS2;
- wherein the four terminals include a source terminal that is serially connected to a switch device for selection or the non-volatile memory cell.
- View Dependent Claims (17, 18, 19)
Specification