Memory device having at least a first and a second operating mode

• US 7,210,015 B2
• Filed: 06/15/2005
• Issued: 04/24/2007
• Est. Priority Date: 05/07/1996
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard Maurice, Hampel, Craig Edward, Ware, Frederick Abbot, Horowitz, Mark Alan
• Primary Examiner(s): Ellis; Kevin L.
• Application Number:
  US11/153,679
• Publication Number:
  US 20050243612A1
• Time in Patent Office: 678 Days
• Field of Search: 711/104, 711/105, 711/167, 711/168, 711/169, 711/400, 713/400
• US Class Current: 711/167
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.

Claims

1. An integrated circuit memory device comprising:

a latch circuit to load an address using a first control signal, wherein a first signal level transition of the first control signal is used to load the address;

a memory array to store data at a memory location that is based on the address;

an output buffer to output the data after a period of time from the first signal level transition; and

a register to store a value that specifies between at least a first mode and a second mode, wherein;

when the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition; and

when the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal,

wherein the memory array includes dynamic memory cells to store the data.

2. The integrated circuit memory device of claim 1, further including:

a clock buffer to receive the external clock signal; and

a control input to receive a signal to activate the clock buffer.

3. The integrated circuit memory device of claim 1, wherein the address is a column address, the latch circuit to further receive a row address, wherein both the row address and the column address specify the memory location.

4. The integrated circuit memory device of claim 3, wherein the memory array includes a plurality of banks to store the data, wherein the column address includes bank address information.

5. The integrated circuit memory device of claim 1, further including:

a multiplexer, coupled to the output buffer, the multiplexer to receive the external clock signal and the first control signal, wherein;

during the first mode, the multiplexer couples the first control signal to the output buffer such that the first control signal is used to time the output of the data; and

during the second mode, the multiplexer couples the external clock signal to the output buffer such that the external clock signal is used to time the output of the data.

6. The integrated circuit memory device of claim 5, further including a delay lock loop coupled to the multiplexer and the output buffer, the delay lock loop to receive the external clock signal and generate an internal clock signal, wherein during a third mode the multiplexer couples the internal clock signal to the output buffer such that the internal clock signal is used to time the output of the data.

7. The integrated circuit memory device of claim 6, wherein the value further specifies between the first mode, the second mode, and the third mode.

8. The integrated circuit device of claim 1, wherein when the value specifies the second mode, the output buffer outputs data synchronously with respect to the external clock signal via an internal clock signal generated by a delay lock loop that receives the external clock signal.

9. An integrated circuit memory device comprising:

a memory array having dynamic memory cells to store data;

a clock buffer to receive an external clock signal;

an input buffer to receive a control signal;

an output buffer to output the data in response to the control signal, wherein the data is output after a number of clock cycles from when the control signal is received; and

a register to store a value to indicate a mode of operation of the integrated circuit memory device, the value to indicate whether the integrated circuit memory device operates in at least one of a first mode and a second mode, wherein;

when the value indicates the first mode of operation, the output buffer outputs the data using the external clock signal; and

when the value indicates the second mode of operation, the output buffer outputs the data in response to address transitions.

10. The integrated circuit memory device of claim 9, wherein the first mode of operation is a synchronous mode of operation and the second mode of operation is an asynchronous mode of operation.

11. The integrated circuit memory device of claim 9, wherein the value further indicates whether the integrated circuit memory device operates in a third mode of operation, wherein during the third mode of operation, the output buffer outputs the data using an internal clock signal that is delay locked to the external clock signal.

12. The integrated circuit memory device of claim 9, further including:

a multiplexer, coupled to the output buffer, to receive the external clock signal and the control signal, wherein;

when the value indicates the first mode of operation, the multiplexer couples the external clock signal to the output buffer such that the external clock signal is used to time the output of the data; and

when the value indicates the second mode of operation, the multiplexer couples the control signal to the output buffer such that the control signal is used to time the output of the data.

13. The integrated circuit memory device of claim 9, further including a pin to receive a clock enable signal, wherein a falling edge of the clock enable signal enables the clock buffer to receive the external clock signal.

14. An integrated circuit memory device comprising:

a memory array having a plurality of banks to store data;

a clock buffer to receive an external clock signal;

an output buffer to output the data after a period of time from receipt of a transition in a control signal; and

a register to store a value that indicates a mode of operation of the integrated circuit memory device, the mode of operation selected from between at least a synchronous mode of operation and an asynchronous mode of operation, wherein;

when the value indicates the synchronous mode of operation, the output buffer outputs the data in response to a transition of the external clock signal; and

when the value indicates the asynchronous mode of operation, the output buffer outputs the data in response to the control signal;

wherein each bank of the plurality of banks in the memory array includes dynamics memory cells, wherein the data is stored in dynamic memory cells identified by a memory address, wherein the memory address includes a bank address.

15. The integrated circuit memory device of claim 14, further including:

a multiplexer, coupled to the output buffer, to receive the external clock signal and the control signal, wherein;

when the value indicates the synchronous mode of operation, the multiplexer couples the external clock signal to the output buffer such that the external clock signal is used to time the output of the data; and

when the value indicates the asynchronous mode of operation, the multiplexer couples the control signal to the output buffer such that the control signal is used to time the output of the data, wherein the control signal is used to receive the memory address.

16. The integrated circuit memory device of claim 15, further including a delay lock loop circuit coupled to the multiplexer and the output buffer, the delay lock loop circuit to receive the external clock signal and generate an internal clock signal, wherein during a mode of operation other than the synchronous mode of operation and the asynchronous mode of operation, the multiplexer couples the internal clock signal to the output buffer such that the internal clock signal is used to time the output of the data.

17. The integrated circuit memory device of claim 14, wherein during the asynchronous mode of operation, the output buffer outputs the data after a period of time from when a falling edge of the control signal is detected, wherein the falling edge is used to sample a memory address.

18. The integrated circuit memory device of claim 17, wherein the memory address is a column address, and the intergrated circuit memory device further comprising an address latch circuit to receive the column address and a row address.

19. A method of operating a memory device having a memory array including dynamic memory cells to store data, the method comprising:

specifying at least one of a first mode of operation and a second mode of operation;

receiving an address using a first control signal;

accessing the data in a location of the memory array specified at least in part by the address;

outputting the data in response to a second control signal that specifies a read transaction;

wherein;

during the first mode of operation, the output buffer outputs the data after a period of time from a transition of the first control signal; and

during the second mode of operation, the output buffer outputs the data after a predetermined number of clock cycles of an external clock signal have transpired from receiving the address, wherein the data is output with reference to transitions of the external clock signal.

20. The method of claim 19, wherein the address is a column address, the method further comprising receiving a row address, wherein both the row address and the column address specify the location of the memory array.

21. The method of claim 19, further including, during a third mode of operation:

generating an internal clock signal that is delay locked with respect to the external clock signal; and

outputting data with reference to transitions of the internal clock signal.

22. The method of claim 21, wherein the first mode of operation is an asynchronous mode of operation and both the second and third modes of operation are synchronous modes of operation.

23. The method of claim 19, further including receiving a third control signal that specifies one of the first mode of operation and the second mode of operation.

24. The method of claim 19, further including storing a value in a register, the value to specify one of the first mode of operation and the second mode of operation.