Current-controlled CMOS logic family
DC CAFCFirst Claim
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1. An apparatus, comprising:
- a first circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process a first signal thereby generating a second signal there from, wherein the first signal is a differential signal;
a second circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process a third signal thereby generating a fourth signal there from, wherein the second signal is a differential signal; and
a third circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to;
receive the second signal;
receive the fourth signal; and
process the second signal and the fourth signal thereby generating a fifth signal there from.
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Abstract
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.
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Citations
20 Claims
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1. An apparatus, comprising:
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a first circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process a first signal thereby generating a second signal there from, wherein the first signal is a differential signal; a second circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process a third signal thereby generating a fourth signal there from, wherein the second signal is a differential signal; and a third circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to; receive the second signal; receive the fourth signal; and process the second signal and the fourth signal thereby generating a fifth signal there from. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus, comprising:
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a first circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive and process a first signal thereby generating a second signal and a third signal there from; a second circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process the second signal thereby generating a fourth signal there from; and a third circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process the third signal thereby generating a fifth signal there from. - View Dependent Claims (10, 11, 12, 13, 14)
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15. An apparatus, comprising:
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a first circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to receive and process a first signal thereby generating a second signal and a third signal there from; a second circuit block, implemented using conventional complementary metal-oxide semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process the second signal thereby generating a fourth signal there from; a third circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process the third signal thereby generating a fifth signal there from. a fourth circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to; receive the fourth signal; receive the fifth signal; and process the fourth signal and the fifth signal thereby generating a sixth signal there from. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification