Lateral semiconductor device using trench structure and method of manufacturing the same

• US 7,242,058 B2
• Filed: 06/17/2005
• Issued: 07/10/2007
• Est. Priority Date: 07/01/2004
• Status: Active Grant

• Current Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Risaki, Tomomitsu
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/155,960
• Publication Number:
  US 20060001085A1
• Time in Patent Office: 753 Days
• Field of Search: 438/242, 247/330, 247/E27.091, 437/243
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device has a semiconductor substrate and a trench region having at least one trench disposed on a surface of the semiconductor substrate and having a trench length, a trench width and a trench depth. A well region is disposed in the substrate and surrounds the trench region. A source region and a drain region are disposed above the well region and around respective inner walls of the trench. The source region and the drain region are disposed in confronting relation relative one another and have a conductivity type different from a conductivity type of the well region. A gate insulating film is disposed on the surface of the semiconductor substrate and on an inner base and the inner walls of the trench. A gate electrode is disposed on the gate insulating film. A length of the gate electrode is shorter than the trench length and equal to a distance between the source region and the drain region.

Claims

1. A semiconductor device, comprising:

a first trench region having a plurality of trenches formed on a surface of a semiconductor substrate;

a second trench region and a third trench region disposed on the same plane as a bottom surface of a concave portion of the first trench region so that the second trench region and the third trench region contact respective opposite ends of the first trench region in the lengthwise direction thereof;

a well region formed in the first trench region, the second trench region, and the third trench region;

a gate insulating film disposed in the first trench region;

a gate electrode disposed on the gate insulating film, the gate electrode having a length extending in a direction generally parallel to lengthwise directions of the trenches;

a source region having a conductivity type different from a conductivity type of the well region, the source region being disposed above the well region and in the second trench region and in a first portion of the first trench region; and

a drain region having the same conductivity type as that of the source region, the drain region being disposed above the well region and in the third trench region and in a second portion of the first trench region.

2. A semiconductor device according to claim 1;

wherein the semiconductor device has a DDD (double doped drain) structure.

3. A semiconductor device according to claim 1;

wherein the semiconductor device has an LDMOS (laterally diffused metal oxide semiconductor) structure.

4. A semiconductor device according to claim 1;

wherein a width of a convex portion in the first trench region is approximately 1,000 Å

.

5. A semiconductor device according to claim 2;

wherein a width of a convex portion in the first trench region is approximately 1,000 Å

.

6. A semiconductor device according to claim 3;

wherein a width of a convex portion in the first trench region is approximately 1,000 Å

.

7. A semiconductor device according to claims 1;

wherein the semiconductor device is formed by a semiconductor process that implements twin well technology.

8. A semiconductor device according to claim 2;

wherein the semiconductor device is formed by a semiconductor process that implements twin well technology.

9. A semiconductor device according to claim 3;

wherein the semiconductor device is formed by a semiconductor process that implements twin well technology.

10. A semiconductor device according to claim 4;

wherein the semiconductor device is formed by a semiconductor process that implements twin well technology.

11. A semiconductor device according to claim 5;

wherein the semiconductor device is formed by a semiconductor process that implements twin well technology.

12. A semiconductor device according to claim 6;

wherein the semiconductor device is formed by a semiconductor process that implements twin well technology.

13. A semiconductor device comprising:

a semiconductor substrate;

a trench region having at least one trench disposed on a surface of the semiconductor substrate and having a trench length, a trench width and a trench depth;

a well region disposed in the substrate and surrounding the trench region;

a source region and a drain region disposed above the well region and disposed around inner walls of the trench, and the source region and the drain region being disposed in confronting relation relative one another and having a conductivity type different from a conductivity type of the well region;

a gate insulating film disposed on the surface of the semiconductor substrate and on an inner base and the inner walls of the trench; and

a gate electrode disposed on the gate insulating film, a length of the gate electrode being shorter than the trench length and equal to a distance between the source region and the drain region.

14. A semiconductor device according to claim 13;

wherein the semiconductor device has a double doped drain structure.

15. A semiconductor device according to claim 13;

wherein the semiconductor device has a laterally diffused metal oxide semiconductor structure.

16. A semiconductor device according to claim 13;

wherein a width of a convex portion of the trench is approximately 1,000 Å

.

17. A semiconductor device comprising:

a semiconductor substrate;

a plurality of trenches formed on a surface of the semiconductor substrate, each of the trenches having a concave portion and a convex portion;

a gate insulating film disposed on the concave portions and the convex portions of the trenches;

a gate electrode disposed on the gate insulating film;

a source region and a drain region each having upper surfaces disposed in coplanar relation to base surfaces of the concave portions of the trenches; and

a well region disposed under the source and drain regions.

18. A semiconductor device according to claim 17;

wherein the trench has a length extending in a direction generally parallel to a length direction of the gate electrode.

19. A semiconductor device according to claim 18;

wherein the length of the gate electrode is shorter than the length of the trench; and

wherein the source region and the drain region are spaced apart a distance equal to the length of the gate.