Multiple oxide thicknesses for merged memory and logic applications

• US 7,271,467 B2
• Filed: 08/30/2004
• Issued: 09/18/2007
• Est. Priority Date: 08/31/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): Lee; Eugene
• Application Number:
  US10/929,281
• Publication Number:
  US 20050023593A1
• Time in Patent Office: 1,114 Days
• Field of Search: 257/627, 257/628, 257/301, 257/302, 257/296, 257/300
• US Class Current: 257/627
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO₂ on a top surface of a silicon wafer and a trench layer of SiO₂ on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.

Claims

1. A semiconductor device, comprising:

a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the logic device having a logic gate separated from the top surface by a logic gate oxide; and

an EEPROM (Electronically Erasable Programmable Read Only Memory) device formed on a trench wall of the silicon wafer, the EEPROM device having an EEPROM gate separated from the trench wall by a EEPROM gate oxide, wherein the trench wall has a different order plane-orientation than the top surface and wherein a thickness of the logic gate oxide is different from a thickness of the EEPROM gate oxide.

2. The semiconductor device of claim 1, wherein the thickness of the EEPROM gate oxide is greater than the thickness of the logic gate oxide.

3. The semiconductor device of claim 1, wherein the thickness of EEPROM gate oxide is approximately 30% thicker than the thickness of logic gate oxide.

4. The semiconductor device of claim 1, wherein the trench wall has a (311) crystal plane orientation.

5. The semiconductor device of claim 1, wherein the trench wall has a (511) crystal plane orientation.

6. The semiconductor device of claim 1, wherein the logic gate oxide is approximately 70 Angstroms, and wherein the EEPROM gate oxide is approximately 100 Angstroms.

7. An electronic system comprising:

a processor; and

a flash memory device including;

a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (111) crystal plane orientation, the logic device having a logic gate separated from the top surface by a logic gate oxide; and

a flash memory cell formed on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystal plane orientation, the flash memory cell having a flash gate separated from the trench wall by a flash gate oxide, wherein a thickness of the flash gate oxide is different from the logic gate oxide.

8. The electronic system of claim 7, wherein the logic gate oxide thickness is approximately 70 Angstroms.

9. The electronic system of claim 7, wherein the flash gate oxide thickness is approximately 100 Angstroms.

10. The electronic system of claim 7, wherein the logic device has an operating voltage of less than 2.5 volts.

11. The electronic system of claim 7, wherein the flash memory cell has an operating voltage of less than 3.5 volts.

12. The electronic system of claim 7, wherein the logic gate oxide thickness is approximately 70 Angstroms, wherein the flash gate oxide thickness is approximately 100 Angstroms, wherein the logic device has an operating voltage of less than 2.5 volts, and wherein the flash memory cell has an operating voltage of less than 3.5 volts.

13. An electronic system comprising:

a processor; and

a decode circuit, comprising;

a logic circuit formed on a top surface of a silicon wafer, wherein the top layer as a (110) crystal plane orientation, the logic circuit having a logic gate separated from the top layer by a logic gate oxide; and

an EEPROM (Electronically Erasable Programmable Read Only Memory) device formed on a trench wall of the silicon wafer, the EEPROM device having an EEPROM gate separated from the trench wall by a EEPROM gate oxide, wherein the trench wall has a different order plane-orientation than the top surface and wherein a thickness of the EEPROM gate oxide is different from a thickness of the logic gate oxide.

14. The electronic system of claim 13, wherein the thickness of EEPROM gate oxide is approximately 30% thicker than the thickness of logic gate oxide.

15. The electronic system of claim 13, wherein the trench wall has a (311) crystal plane orientation.

16. The electronic system of claim 13, wherein the trench wall has a (511) crystal plane orientation.

17. The electronic system of claim 13, wherein the logic gate oxide thickness is approximately 70 Angstroms, wherein the EEPROM gate oxide thickness is approximately 100 Angstroms, wherein the logic circuit has an operating voltage of less than 2.5 volts, and wherein the EEPROM device has an operating voltage of less than 3.5 volts.

18. A semiconductor device, comprising,

a logic device formed on a top surface of a silicon wafer having a (100) crystal plane orientation and a top gate oxide;

and

an EEPROM device formed on a trench wall of the silicon wafer, the trench wall having a (110) crystal plane orientation and a trench gate oxide.

19. The semiconductor device of claim 18 further comprising the trench gate oxide is different from the top gate oxide, and the top gate oxide and the trench gate oxide are formed simultaneously.

20. The semiconductor device of claim 19 further comprising the trench gate oxide approximately 30% thicker than the top gate oxide.