Please download the dossier by clicking on the dossier button x
×

Multiple oxide thicknesses for merged memory and logic applications

  • US 7,271,467 B2
  • Filed: 08/30/2004
  • Issued: 09/18/2007
  • Est. Priority Date: 08/31/1999
  • Status: Expired due to Term
First Claim
Patent Images

1. A semiconductor device, comprising:

  • a logic device formed on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, the logic device having a logic gate separated from the top surface by a logic gate oxide; and

    an EEPROM (Electronically Erasable Programmable Read Only Memory) device formed on a trench wall of the silicon wafer, the EEPROM device having an EEPROM gate separated from the trench wall by a EEPROM gate oxide, wherein the trench wall has a different order plane-orientation than the top surface and wherein a thickness of the logic gate oxide is different from a thickness of the EEPROM gate oxide.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×