Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension
First Claim
1. A method of forming a PMOSFET, comprising the steps of:
- providing an SOI wafer having a buried insulator layer and a SOI layer above said buried insulator layer;
forming a layer of gate insulator over said SOI layer;
forming a transistor gate over said SOI layer having a channel underneath said gate;
forming insulator sidewalls on first and second sides of said gate;
epitaxially forming a doped layer containing a dopant on said SOI layer and adjacent to said insulator sidewalls;
diffusing said dopant into said SOI layer from said doped layer, thereby producing compressive stress in the horizontal direction parallel to an SOI surface and tensile stress in a vertical direction normal to said SOI surface in said channel;
in which said step of diffusing continues until germanium reaches a bottom surface of said SOI layer; and
completing said PMOSFET.
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Accused Products
Abstract
P-type MOSFETs (PMOSFETs) are formed by encapsulating the gate with an insulator and depositing a germanium containing layer outside the sidewalls, then diffusing the germanium into the silicon-on-insulator layer or bulk silicon by annealing or by oxidizing to form graded embedded silicon-germanium source-drain and/or Extension (geSiGe-SDE). For SOI devices, the geSiGe-SDE is allowed to reach the buried insulator to maximize the stress in the channel of SOI devices, which is beneficial for ultra-thin SOI devices. Graded germanium profiles provide a method to optimize stress in order to enhance device performance. The geSiGe-SDE creates a compressive stress in the horizontal direction (parallel to the gate dielectric surface) and tensile stress in the vertical direction (normal to the gate dielectric surface) in the channel of the PMOSFET, therebyforming a structure that enhances PMOSFET performance.
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Citations
15 Claims
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1. A method of forming a PMOSFET, comprising the steps of:
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providing an SOI wafer having a buried insulator layer and a SOI layer above said buried insulator layer; forming a layer of gate insulator over said SOI layer; forming a transistor gate over said SOI layer having a channel underneath said gate; forming insulator sidewalls on first and second sides of said gate; epitaxially forming a doped layer containing a dopant on said SOI layer and adjacent to said insulator sidewalls; diffusing said dopant into said SOI layer from said doped layer, thereby producing compressive stress in the horizontal direction parallel to an SOI surface and tensile stress in a vertical direction normal to said SOI surface in said channel;
in which said step of diffusing continues until germanium reaches a bottom surface of said SOI layer; andcompleting said PMOSFET. - View Dependent Claims (2)
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3. A method of forming a PMOSFET, comprising the steps of:
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providing an SOI wafer having a buried insulator layer and a SOI layer above said buried insulator layer; forming a layer of gate insulator over said SOI layer; forming a transistor gate over said SOI layer having a channel underneath said gate; forming insulator sidewalls on first and second sides of said gate; epitaxially forming a doped layer containing a dopant on said SOI layer and adjacent to said insulator sidewalls; diffusing said dopant into said SOI layer from said doped layer, thereby producing compressive stress in the horizontal direction parallel to an SOI surface and tensile stress in a vertical direction normal to said SOI surface in said channel;
in which said step of diffusing stops before germanium reaches a bottom surface of said SOI layer; andcompleting said PMOSFET.
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4. A method of forming a PMOSFET, comprising the steps of:
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providing an SOI wafer having a buried insulator layer and a SOI layer above said buried insulator layer; forming a layer of gate insulator over said SOI layer; forming a transistor gate over said SOI layer having a channel underneath said gate; forming insulator sidewalls on first and second sides of said gate; epitaxially forming a doped layer containing a dopant on said SOI layer and adjacent to said insulator sidewalls; diffusing said dopant into said SOI layer from said doped layer, thereby producing compressive stress in the horizontal direction parallel to an SOI surface and tensile stress in a vertical direction normal to said SOI surface in said channel;
in which said doped layer is SiGe having a germanium concentration of greater than atomic number 20%; andcompleting said PMOSFET.
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5. A method of forming a PMOSFET, comprising the steps of:
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providing an SOI wafer having a buried insulator layer and a SOI layer above said buried insulator layer; forming a layer of gate insulator over said SOI layer; forming a transistor gate over said SOI layer having a channel underneath said gate; forming insulator sidewalls on first and second sides of said gate; epitaxially forming a doped layer containing a dopant on said SOI layer and adjacent to said insulator sidewalls; diffusing said dopant into said SOI layer from said doped layer, thereby producing compressive stress in the horizontal direction parallel to an SOI surface and tensile stress in a vertical direction normal to said SOI surface in said channel;
further comprising growing a layer of thermal oxide on said doped layer, thereby diffusing said dopant in the doped layer into said SOI layer; andcompleting said PMOSFET. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A method of forming a PMOSFET, comprising the steps of:
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providing a bulk silicon wafer; forming a layer of gate insulator over said bulk silicon; forming a transistor gate over said bulk silicon having a channel underneath said gate; forming insulator sidewalls on first and second sides of said gate; epitaxially forming a doped layer containing germanium or impurity on said bulk silicon and adjacent to said insulator sidewalls; diffusing germanium into said bulk silicon from said germanium doped layer, thereby producing compressive stress in horizontal direction (parallel to SOI surface) and tensile stress in vertical direction (in normal of SOI surface) in said channel;
in which said dopant layer is SiGe with a germanium concentration of greater than atomic number 20%; andcompleting said PMOSFET.
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12. A method of forming a PMOSFET, comprising the steps of:
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providing a bulk silicon wafer; forming a layer of gate insulator over said bulk silicon; forming a transistor gate over said bulk silicon having a channel underneath said gate; forming insulator sidewalls on first and second sides of said gate; epitaxially forming a doped layer containing germanium or impurity on said bulk silicon and adjacent to said insulator sidewalls; diffusing germanium into said bulk silicon from said germanium doped layer, thereby producing compressive stress in horizontal direction (parallel to SOI surface) and tensile stress in vertical direction (in normal of SOI surface) in said channel;
further comprising growing a layer of thermal oxide on said dopant layer, thereby diffusing said dopant into said bulk silicon; andcompleting said PMOSFET. - View Dependent Claims (13, 14, 15)
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Specification