States encoding in multi-bit flash cells
First Claim
1. A method of storing N bits of data, comprising the steps of:
- (a) providing ┌
N/M┐
cells; and
(b) programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies a criterion selected from the group consisting of;
(i) a number of threshold voltage comparisons for sequentially and statically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1,(ii) a maximum number of threshold voltage comparisons for statically reading any one of said M bits is minimized,(iii) a minimum number of threshold voltage comparisons for statically reading any one of said M bits is minimized,(iv) a maximum number of threshold voltage comparisons for statically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for statically reading any one of said M bits by at most 1,(v) a number of threshold voltage comparisons for sequentially and dynamically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1,(vi) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized,(vii) a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized, and(viii) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits by at most 1;
wherein M is at least 3.
4 Assignments
0 Petitions
Accused Products
Abstract
N data bits are stored in ┌N/M┐ cells by programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies one of the following criteria: Either the number of threshold voltage comparisons needed to read all M bits sequentially is at most 1 more than the smallest such number, or the largest number of threshold voltage comparisons needed to read any bit is minimized, or the smallest number of threshold voltage comparisons needed to read any bit is minimized, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit statically is at most 1 more than the smallest such difference, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit dynamically is minimized.
134 Citations
78 Claims
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1. A method of storing N bits of data, comprising the steps of:
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(a) providing ┌
N/M┐
cells; and(b) programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies a criterion selected from the group consisting of; (i) a number of threshold voltage comparisons for sequentially and statically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1, (ii) a maximum number of threshold voltage comparisons for statically reading any one of said M bits is minimized, (iii) a minimum number of threshold voltage comparisons for statically reading any one of said M bits is minimized, (iv) a maximum number of threshold voltage comparisons for statically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for statically reading any one of said M bits by at most 1, (v) a number of threshold voltage comparisons for sequentially and dynamically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1, (vi) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized, (vii) a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized, and (viii) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits by at most 1; wherein M is at least 3. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59)
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60. A memory device comprising:
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(a) a memory that includes K cells; and (b) a controller operative to store N bits of data in said cells by programming each said cell with up to M=┌
N/K┐
of said bits according to a valid, nonserial bit ordering that satisfies a criterion selected from the group consisting of;(i) a number of threshold voltage comparisons for sequentially and statically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1, (ii) a maximum number of threshold voltage comparisons for statically reading any one of said M bits is minimized, (iii) a minimum number of threshold voltage comparisons for statically reading any one of said M bits is minimized, (iv) a maximum number of threshold voltage comparisons for statically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for statically reading any one of said M bits by at most 1, (v) a number of threshold voltage comparisons for sequentially and dynamically reading said M bits exceeds a minimum said number of threshold voltage comparisons by at most 1, (vi) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized, (vii) a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits is minimized, and (viii) a maximum number of threshold voltage comparisons for dynamically reading any one of said M bits exceeds a minimum number of threshold voltage comparisons for dynamically reading any one of said M bits by at most 1; wherein M is at least 3.
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61. A method of storing N bits of data, comprising the steps of:
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(a) providing ┌
N/M┐
cells; and(b) programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies a criterion selected from the group consisting of; (i) a total number of transitions in said bit ordering is a minimum said number of transitions, (ii) said total number of transitions in said bit ordering exceeds a minimum said number of transitions by 1, (iii) a maximum said number of transitions in said bit ordering is a minimum said maximum number of transitions, (iv) a minimum said number of transitions in said bit ordering is a minimum said minimum number of transitions, (v) said bit ordering is such that all M bits have a common number of transitions, and (vi) said bit ordering is such that a number of transitions of any bit differs from a number of transitions of any other bit by at most 1; wherein M is at least 3. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77)
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78. A memory device comprising:
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(a) a memory that includes K cells; and (b) a controller operative to store N bits of data in said cells by programming each said cell with up to M=┌
N/K┐
of said bits according to a valid, nonserial bit ordering that satisfies a criterion selected from the group consisting of;(i) a total number of transitions in said bit ordering is a minimum said number of transitions, (ii) said total number of transitions in said bit ordering exceeds a minimum said number of transitions by 1, (iii) a maximum said number of transitions in said bit ordering is a minimum said maximum number of transitions, (iv) a minimum said number of transitions in said bit ordering is a minimum said minimum number of transitions, (v) said bit ordering is such that all M bits have a common number of transitions, and (vi) said bit ordering is such that a number of transitions of any bit differs from a number of transitions of any other bit by at most 1; wherein M is at least 3.
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Specification