Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements

• US 7,325,123 B2
• Filed: 03/07/2003
• Issued: 01/29/2008
• Est. Priority Date: 03/22/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation), Much Shelist Freed Ament & Rubenstein, PC
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L., Hogenauer, Eugene, Scheuermann, Walter James
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US10/384,486
• Publication Number:
  US 20030154357A1
• Time in Patent Office: 1,789 Days
• Field of Search: None
• US Class Current: 712/37
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit having computational elements. As least one of the computational elements has a fixed architecture. An interconnection network is coupled to a first group of the computational elements to configure the first group for a first operation. An interconnection network is coupled to a second group of computational elements to configures the second group for a second operation.

Claims

1. An integrated circuit, comprising:

a first plurality of computational elements, at least one computational element of the first plurality of computational elements having a fixed architecture;

a first interconnection network coupled to the first plurality of computational elements and adapted to configure the first plurality of computational elements for a first data operation of a plurality of data operations, in response to first configuration information;

a first memory element coupled to the first interconnection network and adapted to store the first configuration information;

a second plurality of computational elements, at least one computational element of the second plurality of computational elements having a fixed architecture;

a second interconnection network coupled to the second plurality of computational elements arid adapted to configure the second plurality of computational elements for a second data operation of the plurality of data operations, in response to second configuration information;

a second memory element coupled to the second interconnection network and adapted to store the second configuration information;

a processor element; and

a third interconnection network adapted to selectively transfer data or control between or among the first and second pluralities of computational elements and the processor element.

2. The integrated circuit of claim 1, wherein the first interconnection network is further adapted to reconfigure the first plurality of computational elements in response to third configuration information and the second interconnection network is further adapted to reconfigure the second plurality of computational elements in response to fourth configuration information.

3. The integrated circuit of claim 1, wherein the processor element is a reduced instruction set (RISC) processor, a digital signal processor, a microprocessor, or a finite state machine.

4. The integrated circuit of claim 1, wherein the first and second configuration information are stored as corresponding tables in the first and second memory elements, respectively.

5. The integrated circuit of claim 1, wherein the first and second pluralities of computational elements further comprise different pluralities of fixed and differing computational elements.

6. The integrated circuit of claim 1, wherein the first and second pluralities of computational elements further comprise at least one non-fixed or internally configurable computational element.

7. The integrated circuit of claim 6, wherein the at least one configurable computational element further comprises a configurable gate array, a configurable function array, or a configurable logic block.

8. The integrated circuit of claim 1, further comprising:

a configuration network adapted to selectively transfer the first and second configuration information to the first and second memory elements, respectively.

9. The integrated circuit of claim 8, wherein the configuration network is a serial bus.

10. The integrated circuit of claim 1, further comprising:

a configuration network adapted to selectively transfer the first and second configuration information to the first and second interconnection networks, respectively.

11. The integrated circuit of claim 1, wherein the third interconnection network is further adapted to selectively and respectively transfer the first and second configuration information to the first and second pluralities of computational elements, to the first and second interconnection networks, or to the first and second memory elements.

12. The integrated circuit of claim 1, wherein the third interconnection network is indirectly coupled to the first and second pluralities of computational elements through the respective first and second interconnection networks.

13. The integrated circuit of claim 12, wherein the third interconnection network is adapted to selectively transfer data or control to or from the first or second pluralities of computational elements through the respective first and second interconnection networks.

14. The integrated circuit of claim 1, wherein the first, second and third interconnection networks further comprise a plurality of switching elements adapted to selectively circuit switch data to or from the first and second pluralities of computational elements.

15. The integrated circuit of claim 14, wherein the plurality of switching elements comprises multiplexers or demultiplexers.

16. The integrated circuit of claim 14, wherein the plurality of switching elements are adapted to couple selected data outputs and selected data inputs of the first or second pluralities of computational elements and to maintain the data output and data input couplings until a subsequent reconfiguration of the first, second or third interconnection networks.

17. The integrated circuit of claim 1, wherein the third interconnection network is further adapted to selectively route a plurality of data packets to the first and second pluralities of computational elements using a corresponding address field of each data packet.

18. An integrated circuit, comprising:

pluralities of fixed and differing computational elements; and

a hierarchical interconnection network comprising a first interconnection network and a plurality of second interconnection networks, the first interconnection network adapted to selectively transfer data or control between or among the pluralities of fixed and differing computational elements, and each second interconnection network of the plurality of second interconnection networks coupled to a corresponding plurality of fixed and differing computational elements and adapted to independently configure the corresponding plurality of fixed and differing computational elements, in response to corresponding configuration information, for a corresponding data operation of a plurality of data operations.

19. The integrated circuit of claim 18, wherein each second interconnection network is further adapted to reconfigure the corresponding plurality of fixed and differing computational elements for a different data operation in response to additional corresponding configuration information.

20. The integrated circuit of claim 18, wherein at least two of the pluralities of fixed and differing computational elements comprise different arrays of fixed and differing computational elements.

21. The integrated circuit of claim 18, further comprising:

a processor element coupled to the first interconnection network, wherein the processor element is a reduced instruction set (RISC) processor, a digital signal processor, a microprocessor, or a finite state machine.

22. The integrated circuit of claim 18, further comprising:

a plurality of memory elements, a corresponding memory element of the plurality of memory elements coupled to a corresponding second interconnection network and adapted to store corresponding configuration information as a look up table.

23. The integrated circuit of claim 22, further comprising:

a configuration bus adapted to selectively transfer corresponding configuration information to the corresponding memory element.

24. The integrated circuit of claim 22, wherein the first interconnection network is further adapted to selectively transfer corresponding configuration information to the corresponding memory element.

25. The integrated circuit of claim 18, wherein the first interconnection network is indirectly coupled to the pluralities of fixed and differing computational elements through the corresponding second interconnection networks.

26. The integrated circuit of claim 18, wherein the first and second interconnection networks further comprise a plurality of switching elements adapted to selectively circuit switch data to or from the pluralities of fixed and differing computational elements.

27. The integrated circuit of claim 26, wherein the plurality of switching elements comprise multiplexers or demultiplexers.

28. The integrated circuit of claim 26, wherein the plurality of switching elements are adapted to couple selected data outputs and selected data inputs of the first or second pluralities of computational elements and to maintain the data output and data input couplings until a subsequent reconfiguration of the first, second or third interconnection networks.

29. The integrated circuit of claim 18, wherein the first interconnection network is further adapted to selectively route a plurality of discrete data packets to the pluralities of fixed and differing computational elements using a corresponding address field of each data packet.

30. The integrated circuit of claim 18, wherein at least one computational element of the pluralities of fixed and differing computational elements is parameterizable.

31. A method of operating the integrated circuit of claim 18, comprising:

in response to first corresponding configuration information and through a corresponding second interconnection network, configuring a first plurality of computational elements of the pluralities of fixed and differing computational elements for performance of a first corresponding data operation of the plurality of data operations;

in response to second corresponding configuration information and through another corresponding second interconnection network, independently configuring a second plurality of computational elements of the pluralities of fixed and differing computational elements for performance of a second, different corresponding data operation of the plurality of data operations; and

through the first interconnection network, selectively transferring data or control information to the first and second pluralities of computational elements.

32. An integrated circuit, comprising:

a first plurality of heterogeneous computational elements;

a first interconnection network coupled to the first plurality of heterogeneous computational elements and adapted, in response to first configuration information, to configure the first plurality of heterogeneous computational elements to form a first circuit;

a second plurality of heterogeneous computational elements;

a second interconnection network coupled to the second plurality of heterogeneous computational elements and adapted, in response to second configuration information, to configure the second plurality of heterogeneous computational elements to form a second, different circuit; and

a third interconnection network adapted to selectively transfer data or control between or among the first and second pluralities of heterogeneous computational elements or the first or second interconnection networks.

33. The integrated circuit of claim 32, wherein the first and second pluralities of heterogeneous computational elements comprise different arrays of fixed and differing computational elements.

34. The integrated circuit of claim 32, wherein the first and second pluralities of heterogeneous computational elements comprise at least one internally configurable computational element and at least one fixed computational element.

35. The integrated circuit of claim 34, wherein the at least one internally configurable computational element further comprises a configurable gate array, a configurable function array, or a configurable logic block.

36. The integrated circuit of claim 32, wherein the first interconnection network is further adapted to reconfigure the first plurality of heterogeneous computational elements to form a third different circuit in response to third configuration information, and the second interconnection network is further adapted to reconfigure the second plurality of heterogeneous computational elements to form a fourth different circuit in response to fourth configuration information.

37. The integrated circuit of claim 32, further comprising:

a processor element coupled to the third interconnection network, wherein the processor element is a reduced instruction set (RISC) processor, a digital signal processor, a microprocessor, or a finite state machine.

38. The integrated circuit of claim 32, further comprising:

a plurality of memory elements, a first memory element of the plurality of memory elements coupled to the first interconnection network and adapted to store the first configuration information as a first look up table and a second memory element of the plurality of memory elements coupled to the second interconnection network and adapted to store the second configuration information as a second look up table.

39. The integrated circuit of claim 38, further comprising:

a configuration bus adapted to selectively transfer the first and second configuration information to the first and second memory elements, respectively.

40. The integrated circuit of claim 32, wherein the first and second interconnection networks further comprise a plurality of switching elements adapted to selectively circuit switch data to or from the first or second pluralities of heterogeneous computational elements, and wherein the plurality of switching elements comprise multiplexers or demultiplexers.

41. The integrated circuit of claim 32, wherein the first and second interconnection networks further comprise a plurality of switching elements adapted to couple selected data outputs and selected data inputs of the first or second pluralities of heterogeneous computational elements and to maintain the data output and data input couplings until a subsequent reconfiguration of the first, second or third interconnection networks.

42. The integrated circuit of claim 32, wherein at least one computational element of the first or second pluralities of heterogeneous computational elements is parameterizable.

43. The integrated circuit of claim 32, wherein the third interconnection network is indirectly coupled to the first and second pluralities of heterogeneous computational elements through the respective first and second interconnection networks.

44. The integrated circuit of claim 32, wherein, the third interconnection network is further adapted to selectively route a plurality of data packets to the first and second pluralities of computational elements using a corresponding address field of each data packet.

45. An integrated circuit, comprising:

a first plurality of different computational elements comprising a first computational element having a first fixed architecture and a second computational element having a second architecture;

a first interconnection network coupled to and adapted to configure the first plurality of different computational elements to form a first circuit in response to first configuration information;

a second plurality of different computational elements comprising a first computational element having the first fixed architecture and a second computational element having the second architecture;

a second interconnection network coupled to and adapted to independently configure the second plurality of different computational elements to form a second, different circuit in response to second configuration information; and

a third interconnection network adapted to selectively transfer data and control information between or among the first and second pluralities of heterogeneous computational elements or the first or second interconnection networks.

46. An integrated circuit, comprising:

a first plurality of heterogeneous computational elements, at least one computational element of the first plurality of heterogeneous computational elements having a first fixed architecture;

a first interconnection network adapted to configure the first plurality of heterogeneous computational elements using first configuration information to provide a first configuration;

a second plurality of heterogeneous computational elements, at least one computational element of the second plurality of heterogeneous computational elements having a second, different architecture;

a second, interconnection network adapted to separately configure the second plurality of heterogeneous computational elements using second configuration information to provide a second, different configuration; and

a third interconnection network configurable to selectively transfer data or control between or among the first and second pluralities of heterogeneous computational elements or the first or second interconnection networks.