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Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus

  • US 7,353,362 B2
  • Filed: 07/25/2003
  • Issued: 04/01/2008
  • Est. Priority Date: 07/25/2003
  • Status: Active Grant
First Claim
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1. A self-contained microprocessor subsystem for use in a System-on-chip (SoC) integrated circuit (IC) comprising a processor device, a SoC IC communications bus device and standardized components for enabling communications, said self-contained microprocessor sub-system comprising:

  • a plurality of processor core assemblies, each processor core assembly comprising;

    two or more microprocessor devices each capable of performing operations to implement a given processing functionality;

    a storage device associated with said two or more microprocessor devices in said processor core assembly for storing at least one of data and instructions in said processor core assembly; and

    ,a first local interconnect means residing in each said processor core assembly for enabling communication of instructions and data between said two or more microprocessor devices; and

    ,a second local interconnect means for enabling communications between said plurality of processor core assemblies; and

    ,a bridging device implementing a common macro for enabling send and receive data communications between said second local interconnect means of said self-contained microprocessor sub-system and said SoC IC communications bus device, whereby said plurality of processor core assemblies may communicate with standardized components of said SoC IC via said bridging device, whereby self-contained microprocessor sub-system communications traffic is separated from communications traffic in said SoC without having to accommodate standardized components in said SOC system.

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