Multi-rate, multi-port, gigabit SERDES transceiver
First Claim
1. A transceiver, comprising:
- one or more parallel ports;
multiple serial ports;
a bus connecting said one or more parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports; and
at least one management pad, wherein said management pad is responsive to a data protocol of a first type of standard, and an electrical protocol of a second type of standard,wherein said serial ports are each multi-rate ports capable of selectably operating at one of at least first and second data rates.
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Accused Products
Abstract
A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port Serdes transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.
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Citations
16 Claims
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1. A transceiver, comprising:
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one or more parallel ports; multiple serial ports; a bus connecting said one or more parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports; and at least one management pad, wherein said management pad is responsive to a data protocol of a first type of standard, and an electrical protocol of a second type of standard, wherein said serial ports are each multi-rate ports capable of selectably operating at one of at least first and second data rates. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A transceiver, comprising:
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one or more parallel ports; multiple serial ports, wherein said serial ports convert between a 10 Gigabit Attachment Unit Interface (XAUI) serial protocol and a 10 Gigabit Media Independent Interface (XGMII) parallel protocol using a 10 Gigabit Ethernet Extended Sublaver (XGXS) conversion protocol; and a bus connecting said one or more parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports, wherein said serial ports are each multi-rate ports capable of selectably operating at one of at least first and second data rates.
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13. A transceiver, comprising:
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one or more parallel ports; multiple serial ports, wherein said serial ports operate according to a 10 Gigabit Ethernet Extended Sublaver (XGXS) protocol; and a bus connecting said one or more parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports, wherein said serial ports are each multi-rate ports capable of selectably operating at one of at least first and second data rates.
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14. A transceiver, comprising:
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one or more parallel ports; multiple serial ports, wherein said one or more parallel ports operate at data rates of 1/10 of the data rates of said multiple serial ports; and a bus connecting said one or more parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports, wherein said serial ports are each multi-rate ports capable of selectably operating at one of at least first and second data rates.
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15. A transceiver, comprising:
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one or more parallel ports; multiple serial ports; a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said one or more serial ports; and a configuration block that enables and disables said one or more parallel ports and said multiple serial ports to configure said transceiver; wherein said one or more parallel ports operate at data rates that are a fraction of the data rates of said multiple serial ports. - View Dependent Claims (16)
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Specification