Mechanisms for assuring quality of service for programs executing on a multithreaded processor

• US 7,376,954 B2
• Filed: 10/10/2003
• Issued: 05/20/2008
• Est. Priority Date: 08/28/2003
• Status: Active Grant

• Current Assignee: MIPS Tech, LLC
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Kissell, Kevin D.
• Primary Examiner(s): An, Meng-Al T.
• Assistant Examiner(s): WAI, ERIC CHARLES
• Application Number:
  US10/684,350
• Publication Number:
  US 20050050395A1
• Time in Patent Office: 1,684 Days
• Field of Search: 710/49, 712/245, 712/214, 718/102, 718/104, 718/107
• US Class Current: 718/107
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A mechanism for assuring quality of service for a context in a digital processor has a first scheduling register dedicated to the context, the register having N out of M bits set, and a first scheduler that consults the register to assign issue slots to the context. The first scheduler grants issue slots for the context by referencing the N bits in the first register, and repeats a pattern of assignments of issue slots after referencing the M bits of the first register.

Claims

1. A mechanism for assuring quality of service for a context in a digital processor, comprising:

a first scheduling register dedicated to the context and having N out of M bits set, said bits being indicative of a pattern for assigning instruction issue slots for the context, wherein N and M are integers; and

a first scheduler that consults the bits sequentially to assign issue slots to the context according to whether a bit is set or not set;

wherein the first scheduler repeats the pattern of assignments of issue slots after referencing the M bits of the first scheduling register.

2. The mechanism of claim 1 wherein the granularity of scheduling is determined by adjusting a magnitude of M.

3. The mechanism of claim 1 wherein the number of N bits determines the proportion of issue slots assigned to the context.

4. The mechanism of claim 1 further comprising a specific bit in a status register that, if set, exempts the context from processing any interrupt request.

5. The mechanism of claim 1 wherein the first scheduling register is thirty-two bits wide.

6. The mechanism of claim 1 wherein the context is a virtual processing element (VPE) enabled on the digital processor.

7. The mechanism of claim 1 wherein the context is a program thread.

8. The mechanism of claim 6 further comprising:

a thread disposed within the VPE;

a second scheduling register dedicated to the thread; and

a second scheduler that consults the second scheduling register to assign issue slots to the thread.

9. A method for assuring quality of service for a context in a digital processor, comprising the steps of:

(a) dedicating a register as a scheduling register to the context, the register having M bits, wherein M is an integer;

(b) setting N bits of the register in a pattern desired for issuing instructions for the context, wherein N is an integer; and

(c) scheduling issue slots for the context, wherein said scheduling comprises accessing the pattern of bits sequentially, assigning an issue slot to the context according to whether a bit is set or not set, and repeating after reaching the end of the pattern.

10. The method of claim 9 wherein a granularity of said scheduling is adjusted by adjusting a magnitude of M.

11. The method of claim 9 wherein in step (b) specific patterns of execution for the context are constrained by setting or not setting bits of the scheduling register in consecutive positions as blocks, wherein a block is two or more consecutive positions.

12. The method of claim 9 further comprising a step for assigning and setting a specific bit in a status register that, if set, exempts the context from processing any interrupt request.

13. The method of claim 9 wherein the scheduling register is thirty-two bits wide.

14. The method of claim 9 wherein the context is a virtual processing element (VPE) enabled on the digital processor.

15. The method of claim 9 wherein the context is a program thread.

16. The method of claim 9 wherein the digital processor supports multiple virtual processing elements (VPEs) and each VPE supports one or more program threads, the method comprising assigning at least one scheduling register to a VPE and assigning at least one other scheduling register to a program thread in the VPE.

17. A digital processor for supporting and executing multiple contexts, comprising one or more specific scheduling registers dedicated one-to-one with specific ones of the contexts, and having N of M bits set, said bits being indicative of a specific pattern for granting instruction issue slots for a context, and a scheduler configured to access each of said bits sequentially to grant issue slots to the contexts according to whether a bit is set or not set, and repeat the pattern after reaching the end of the pattern.

18. The digital processor of claim 17 wherein granularity of scheduling is determined by adjusting a magnitude of M.

19. The digital processor of claim 17 wherein the number of bits set in an individual scheduling register compared to M determines the proportion of issue slots assigned to one of the multiple contexts, and setting bits of the scheduling register in consecutive positions as blocks allows repetitive block assignment of issue slots.

20. The digital processor of claim 17 wherein a specific bit in a status register is reserved for interrupt service, such that, if set, an associated context is exempted from servicing interrupt requests.

21. The digital processor of claim 17 wherein one or more of the scheduling registers is thirty-two bits wide.

22. The digital processor of claim 17 enabled to support one or more virtual processing elements (VPEs), and the contexts are VPEs.

23. The digital processor of claim 17 wherein the context is a program thread.

24. The digital processor of claim 17 enabled to support multiple virtual processing elements (VPEs) and each VPE is enabled to support one or more program threads, wherein individual ones of the scheduling registers associate with individual VPEs, and an individual one of the scheduling registers supports an individual program thread in a VPE.

25. A processing system for assuring quality of service for a context, comprising:

at least one processor;

a scheduling register accessible to the processor, dedicated to the context and having N of M bits set in a pattern for assigning instruction issue slots for the context, wherein N and M are integers; and

a scheduler that consults the bits sequentially to assign issue slots to the context according to whether a bit is set or not set;

wherein the scheduler repeats the pattern when reaching the end of the pattern.

26. The system of claim 25 wherein granularity of scheduling is determined by adjusting a magnitude of M.

27. The system of claim 25 wherein the number of bits set compared to M determines the proportion of execution slots assigned to the context, and setting bits of the scheduling register in consecutive positions as blocks allows repetitive block assignment of issue slots.

28. The system of claim 25 further comprising a bus system communicating between the digital processor and one or more input/output (I/O) devices, and a specific bit in a status register that, if set, exempts the context from processing any interrupt request from one of the I/O devices.

29. The system of claim 25 wherein the scheduling register is thirty-two bits wide.

30. The system of claim 25 wherein the context is a virtual processing element (VPE) enabled on the at least one processor.

31. The system of claim 25 wherein the context is a program thread.

32. The system of claim 25 wherein the at least one processor supports multiple virtual processing elements (VPEs) and each VPE supports one or more program threads, the mechanism further comprising at least one scheduling register dedicated to a VPE and at least one other scheduling register dedicated to a program thread in the VPE.

33. A digital storage medium having written thereon a software program code set executable on a digital processor, the code set comprising function code for

reading sequentially bits of a register dedicated to a specific context wherein N out of M of said bits are set, said bits being indicative of a pattern for assigning instruction issue slots for the context, wherein N and M are integers, and

scheduling issue slots for the context, wherein said scheduling comprises assigning issue slots to the associated specific context according to whether each bit is set or not set and repeating the pattern after referencing the M bits of the register.

34. The digital storage medium of claim 33 further comprising a function for recognizing one bit of a dedicated status register as a bit to exempt the associated context from servicing an interrupt request.

35. The digital storage medium of claim 33 wherein the context is a virtual processing element (VPE).

36. The digital storage medium of claim 33 wherein the context is a program thread.

37. A computer-readable storage medium to direct the operations of a computer, comprising:

computer-readable program code for describing a mechanism for assuring quality of service for a context in a digital processor, the program code including;

a first program code segment for describing a scheduling register dedicated to the context and having N out of M bits set, said bits being indicative of a pattern for assigning instruction issue slots for the context, wherein N and M are integers; and

a second program code segment for describing a scheduler that consults the bits sequentially to assign issue slots to the context according to whether a bit is set or not set;

wherein the scheduler repeats the pattern of assignments of issue slots after referencing the M bits of the register.