Top layers of metal for integrated circuits

• US 7,381,642 B2
• Filed: 12/20/2004
• Issued: 06/03/2008
• Est. Priority Date: 09/23/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chou, Chiu-Ming, Lin, Mou-Shiung, Chou, Chien-Kang
• Primary Examiner(s): Everhart; Caridad
• Application Number:
  US11/017,168
• Publication Number:
  US 20060063378A1
• Time in Patent Office: 1,261 Days
• Field of Search: 438/642, 438/666, 438/668, 257/E21.627
• US Class Current: 438/642
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

Claims

1. A method for forming a wirebond and a post-passivation metallization system for an integrated circuit, comprising:

providing a silicon substrate, a MOS device in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said dielectric layer;

forming a first polymer layer on said passivation layer, wherein said forming said first polymer layer comprises depositing a photosensitive polymer on said passivation layer;

forming a second metallization structure over said first polymer layer, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, and wherein said forming said second metallization structure comprises forming a first adhesion/barrier layer over said first polymer layer, forming a first gold layer on said first adhesion/barrier layer, performing a photolithography process to form a photoresist layer on said first gold layer, an opening in said photoresist layer exposing said first gold layer, wherein said photoresist layer has a thickness between 2 and 100 micrometers and wherein said performing said photolithography process comprises using a 1X stepper or aligner, electroplating a second gold layer having a thickness between 2 and 100 micrometers on said first gold layer exposed by said opening in said photoresist layer, removing said photoresist layer, removing said first gold layer not under said second gold layer, and removing said first adhesion/barrier layer not under said second gold layer; and

wirebonding to a contact point of said second metallization structure, wherein said contact point is directly over said polymer layer and directly over said MOS device.

2. The method of claim 1, wherein said first metallization structure comprises a damascene copper and a second adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper.

3. The method of claim 1, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers.

4. The method of claim 1, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.

5. The method of claim 1, wherein said second metallization structure connects multiple separate portions of said first metallization structure.

6. The method of claim 1, wherein said forming said first adhesion/barrier layer comprises sputtering a titanium-tungsten-alloy layer with a thickness between 0.01 and 3 micrometers over said first polymer layer.

7. The method of claim 1, further comprising forming a polymer layer over said second metallization structure.

8. The method of claim 1, wherein said forming said first gold layer comprises sputtering said first gold layer with a thickness between 0.05 and 3 micrometers on said first adhesion/barrier layer.

9. The method of claim 1, wherein said forming said first gold layer comprises a sputtering process.

10. The method of claim 1, wherein said forming said first adhesion/barrier layer comprises a sputtering process.

11. The method of claim 1, wherein said forming said first adhesion/barrier layer comprises forming a titanium-containing layer over said first polymer layer.

12. The method of claim 1, wherein said forming said first adhesion/barrier layer comprises sputtering a titanium layer with a thickness between 0.01 and 3 micrometers over said first polymer layer.

13. A method for forming a post-passivation metallization system for an integrated circuit chip, comprising:

providing a silicon substrate, multiple MOS devices in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure is formed by a process comprising using a 5X stepper or scanner, and wherein said first metallization structure comprises a damascene copper and a first adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper, and a passivation layer over said first metallization structure, wherein said passivation layer comprises a topmost oxynitride layer of said integrated circuit chip;

forming a first polymer layer on said passivation layer, wherein said forming said polymer layer comprises depositing a photosensitive polymer on said passivation layer; and

forming a second metallization structure over said first polymer layer, wherein said second metallization structure connects said multiple MOS devices through separate portions of said first metallization structure, and wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square, wherein said forming said second metallization structure comprises forming a second adhesion/barrier layer over said first polymer layer, forming a seed layer on said second adhesion/barrier layer, performing a photolithography process to form a photoresist layer on said seed layer, an opening in said photoresist layer exposing said seed layer, wherein said performing said photolithography process comprises using a 1X stepper, electroplating a bulk metal layer on said seed layer exposed by said opening in said photoresist layer, wherein the material of said bulk metal layer is the same as that of said seed layer, removing said photoresist layer, removing said seed layer not under said bulk metal layer, and removing said adhesion/barrier layer not under said bulk metal layer.

14. The method of claim 13, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers.

15. The method of claim 13, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.

16. The method of claim 13, further comprising forming a second polymer layer over said second metallization structure.

17. The method of claim 13, wherein said forming said second adhesion/barrier layer comprises sputtering a titanium-tungsten-alloy layer over said first polymer layer.

18. The method of claim 13, wherein said forming said second adhesion/barrier layer comprises sputtering a titanium layer over said first polymer layer.

19. The method of claim 13, wherein said forming said seed layer comprises a sputtering process.

20. The method of claim 13, wherein said electroplating said bulk metal layer comprises electroplating a gold layer with a thickness between 2 and 100 micrometers on said seed layer exposed by said opening in said photoresist layer.

21. The method of claim 13, wherein said forming said adhesion/barrier layer comprises a sputtering process.

22. The method of claim 13, wherein said electroplating said bulk metal layer comprises electroplating a copper layer with a thickness between 2 and 100 micrometers on said seed layer exposed by said opening in said photoresist layer.

23. The method of claim 13, wherein said second metallization structure comprises a wirebonding pad.

24. The method of claim 13, further comprising forming a solder bump connected to said second metallization structure.

25. The method of claim 13, wherein an undercut with an edge of said second adhesion/barrier layer recessed from an edge of said bulk metal layer is between 0.03 and 2 micrometers.

26. The method of claim 20, wherein said electroplating said bulk metal layer comprises electroplating a palladium layer on said seed layer exposed by said opening in said photoresist layer.

27. A circuit component comprising:

an integrated circuit chip comprising a silicon substrate, a MOS device in and on said silicon substrate, a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure and over said dielectric layer, a second metallization structure over said passivation layer, wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square and having a width greater than 2 micrometers, and wherein said second metallization structure comprises a first adhesion/barrier layer over said passivation layer, a first gold layer on said first adhesion/barrier layer, and a second gold layer on said first gold layer, wherein said first adhesion/barrier layer has a thickness between 0.01 and 3 micrometers, said first gold layer has a thickness between 0.05 and 3 micrometers, and said second gold layer has a thickness between 2 and 100 micrometers, and a first polymer layer over said second metallization structure; and

a wirebond connecting a contact point of said second metallization structure to an external circuit, wherein said contact point is directly over said MOS device.

28. The circuit component of claim 27, further comprising a second polymer layer between said second metallization structure and said passivation layer.

29. The circuit component of claim 27, wherein said first adhesion/barrier layer comprises a titanium layer over said passivation layer.

30. The circuit component of claim 27, wherein said first metallization structure comprises a damascene copper and a second adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper.

31. The circuit component of claim 27, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers.

32. The circuit component of claim 27, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.

33. The circuit component of claim 28, wherein said second polymer layer comprises polyimide.

34. The circuit component of claim 28, wherein said second polymer layer has a thickness between 2 and 100 micrometers.

35. The circuit component of claim 27, wherein said first adhesion/barrier layer comprises a titanium-tungsten-alloy layer over said passivation layer.

36. The circuit component of claim 27, wherein an undercut with an edge of said first adhesion/barrier layer recessed from an edge of said first gold layer is between 0.03 and 2 micrometers.

37. An integrated circuit chip comprising:

a silicon substrate;

multiple MOS devices in and on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a passivation layer over said first metallization structure and over said dielectric layer, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip;

a first polymer layer over said passivation layer;

a second metallization structure over said first polymer layer, wherein said second metallization structure connects multiple MOS devices through separate portions of said first metallization structure, wherein said second metallization structure comprises a third metal layer and fourth metal layer over said third metal layer, wherein one of said third and fourth metal layers comprises a first adhesion/barrier layer over said first polymer layer, a seed layer on said first adhesion/barrier layer, and an electroplated metal layer on said seed layer, and wherein said second metallization structure comprises a metal line having a sheet resistance smaller than 7 milliohms per square; and

a second polymer layer between said third and fourth metal layers.

38. The circuit component of claim 37, wherein said first polymer layer has a thickness between 2 and 100 micrometers.

39. The circuit component of claim 37, wherein said first polymer layer comprises polyimide.

40. The circuit component of claim 37, wherein said first polymer layer comprises benzocyclobutene.

41. The circuit component of claim 37, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 micrometers.

42. The integrated circuit chip of claim 37, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.

43. The integrated circuit chip of claim 37, wherein said electroplated metal layer comprises a gold layer with a thickness between 2 and 100 micrometers.

44. The integrated circuit chip of claim 37, wherein said electroplated metal layer comprises a copper layer with a thickness between 2 and 100 micrometers.

45. The integrated circuit chip of claim 37, wherein said electroplated metal layer comprises a palladium layer.

46. The integrated circuit chip of claim 37, wherein said first adhesion/barrier layer comprises titanium.

47. The integrated circuit chip of claim 37, wherein said first metallization structure comprises a damascene copper and a second adhesion/barrier layer under said damascene copper and at a sidewall of said damascene copper.

48. The integrated circuit chip of claim 37, wherein said one of said third and fourth metal layers further comprises a nickel layer on said electroplated metal layer.