Floating gate memory cell with a metallic source/drain and gate, and method for manufacturing such a floating gate memory gate cell
First Claim
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1. A floating gate memory cell, comprising:
- a first layer having a first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions; and
a floating gate layer arranged on the first layer,wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material, andwherein the substrate is made from silicon dioxide.
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Abstract
Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions, and a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.
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Citations
24 Claims
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1. A floating gate memory cell, comprising:
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a first layer having a first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions; and a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material, and wherein the substrate is made from silicon dioxide. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 12)
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10. A floating gate memory cell comprising:
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a first layer having a first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions; and a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material, and wherein the first and second source/drain regions are made from aluminum and the channel region is made from tantalum oxide, or wherein the first and second source/drain regions are made from titanium and the channel region is made from titanium oxide.
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11. A floating gate memory arrangement having a plurality of floating gate memory cells arranged substantially in matrix form, wherein each memory cell comprises:
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a first layer having a first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions; and a floating ante layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material, and wherein an area required for a floating gate memory cell is approximately 4 F2, where F is a minimum feature size that is achieved in a context of a particular technology.
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13. A floating gate memory cell, comprising:
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a substrate; a layer sequence formed on the substrate and having a first source/drain region, a channel region arranged on the first source/drain region, and a second source/drain region arranged on the channel region, wherein the first and second source/drain regions are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material; a first dielectric layer arranged on the surface and side wall regions of the layer sequence and on a portion of the substrate surface that is devoid of the layer sequence; a floating gate layer arranged on side wall regions of the first dielectric layer, wherein the floating gate layer is formed of a metallically conductive material; a second dielectric layer arranged on uncovered surfaces of the first dielectric layer and on the floating gate layer; and a control gate electrode layer arranged on the second dielectric layer, wherein lateral edge sections of the first and second dielectric layers are arranged on the surface of the substrate. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification