Apparatus and method for switchable conditional execution in a VLIW processor
First Claim
1. An apparatus for switchable conditional execution (CE) in a very long instruction word (VLIW) processor, said apparatus comprising:
- one or more instruction decoders being involved in a decode stage for loading and decoding instructions from a fetch unit, said one or more instruction decoders decoding conditional instructions for conditional execution in an energy-saving mode or a high-performance mode;
one or more arithmetic logic units (ALU) with control units, for executing the decoded instructions from said one or more instruction decoders; and
a register file including a plurality of registers for storing and forwarding the executed results of said ALU with control units to said one or more instruction decoders to support said conditional execution;
wherein said apparatus has a special instruction for switching said apparatus between said energy-saving mode and said high-performance mode for scheduling and executing conditional instructions in an in-order-scheduling fashion in said energy-saving mode and in an out-of-order-scheduling fashion in said high-performance mode.
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Abstract
An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and decodes instructions from a fetch unit for decoding and sending the decoded instructions to the ALU with control units for execution. The register file stores and forwards the results on result buses to the decoders. The execution of a VLIW instruction includes a fetch stage, a decode stage, plural execution stages and a write-back stage. The invention has the features of approximate ASIC timing by conditional write-back with the compiler support for the conditional write-back, condition resolved just before write-back, software selective conditional issue and conditional write-back modes, and without hardware interlock/dependence checking for the VLIW processor.
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Citations
15 Claims
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1. An apparatus for switchable conditional execution (CE) in a very long instruction word (VLIW) processor, said apparatus comprising:
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one or more instruction decoders being involved in a decode stage for loading and decoding instructions from a fetch unit, said one or more instruction decoders decoding conditional instructions for conditional execution in an energy-saving mode or a high-performance mode; one or more arithmetic logic units (ALU) with control units, for executing the decoded instructions from said one or more instruction decoders; and a register file including a plurality of registers for storing and forwarding the executed results of said ALU with control units to said one or more instruction decoders to support said conditional execution; wherein said apparatus has a special instruction for switching said apparatus between said energy-saving mode and said high-performance mode for scheduling and executing conditional instructions in an in-order-scheduling fashion in said energy-saving mode and in an out-of-order-scheduling fashion in said high-performance mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A switchable conditional execution method performed in a very long instruction word (VLIW) processor, said method comprising the steps of:
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(a) arranging an instruction format for the VLIW processor to switch between two conditional modes including a conditional issue mode and a conditional write-back mode; (b) decoding conditional instructions using said instruction format for conditional execution in said conditional issue mode or said conditional write-back mode; (c) dividing the execution of a VLIW instruction into a fetch stage, a decode stage, a plurality of execution stages, and a write-back stage; and (d) resolving condition of a conditional instruction in said conditional issue mode at said decode stage, while resolving condition of a conditional instruction in said conditional write-back mode at a last execution stage. - View Dependent Claims (14, 15)
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Specification