Apparatus and method for switchable conditional execution in a VLIW processor

• US 20060288195A1
• Filed: 06/18/2005
• Published: 12/21/2006
• Est. Priority Date: 06/18/2005
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wang, Tengh-Yih, Ma, Yung-Cheng, Kuo, Hsien-Feng
• Granted Patent: US 7,412,591 B2
• Time in Patent Office: Days
• US Class Current: 712/226
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoders loads and decodes said instructions from a fetch unit for decoding and sending the decoded instructions to the ALU with control units for execution. The register file stores and forwards the results on result buses to the decoders. The execution of a VLIW instruction includes a fetch stage, a decode stage, plural execution stages and a write-back stage. The invention has the features of approximate ASIC timing by conditional write-back with the compiler support for the conditional write-back, condition resolved just before write-back., software selective conditional issue and conditional write-back modes, and without hardware interlock/dependence checking for the VLIW processor.

Claims

1. An apparatus for switchable conditional execution (CE) in a very long instruction word (VLIW) processor, which switches the execution of conditional instructions of said processor between a energy-saving mode and a high-performance mode, said apparatus comprising:

one or more instruction decoders being involved in a decode stage for loading and decoding said instructions from a fetch unit;

one or more arithmetic logic unit (ALU) with control units, for executing said decoded instructions from said instruction decoders; and

a register file including a plurality of registers for storing and forwarding the executed results of said ALU with control units to said instruction decoders to support said conditional execution.

2. The apparatus for switchable conditional execution as claimed in claim 1, wherein said processor has an instruction format comprising a CE field for indicating whether said instruction is a conditional instruction, and the source of the condition of said instruction.

3. The apparatus for switchable conditional execution as claimed in claim 2, wherein said source of said condition of said instruction is the least significant bit of a register in said register file.

4. The apparatus for switchable conditional execution as claimed in claim 1, wherein said least significant bits of said registers of said register file are used to broadcast to other parts of said processor.

5. The apparatus for switchable conditional execution as claimed in claim 1, wherein said instruction decoders propagate said CE field to said ALU with control units for execution when executing in said high-performance mode.

6. The apparatus for switchable conditional execution as claimed in claim 1, wherein each ALU with control unit further comprises a functional unit and a recording unit, said functional unit determines whether to execute the opcode of an instruction according to the condition bits broadcasted by said register file, said recording unit records the the CE field propagated from said decode stage for each said execution stage.

7. The apparatus for switchable conditional execution as claimed in claim 1, wherein said decoder blocks said CE field and uses said conditional bits broadcasted by said register file to determine whether the opcode of an instruction should be set as an NOP to save energy when executing in said energy-saving mode.

8. The apparatus for switchable conditional execution as claimed in claim 1, wherein a conditional issue mode is used to execute the conditional instructions when executing in said energy-saving mode, while a conditional write-back mode is used to execute the conditional instructions when executing in said high-performance mode.

9. The apparatus for switchable conditional execution as claimed in claim 8, wherein said conditional issue mode resolves the conditions for conditional instructions at said decode stage, while said conditional write-back mode resolves the conditions for conditional instructions at the last execution stage.

10. The apparatus for switchable conditional execution as claimed in claim 1, wherein for each execution stage, a corresponding output enable line is generated by a corresponding ALU with control unit for indicating a different execution stage when executing in said high-performance mode.

11. The apparatus for switchable conditional execution as claimed in claim 3, wherein said register file further includes a forwarding circuit to broadcast said least significant bits to other parts of said processor.

12. The apparatus for switchable conditional execution as claimed in claim 1, wherein said apparatus is a digital signal processor.

13. The apparatus for switchable conditional execution as claimed in claim 1, wherein said apparatus include a forwarding path to forward the results at said write-back stage to the first execution stage.

14. The apparatus for switchable conditional execution as claimed in claim 1, wherein said register file further has a forwarding circuit to forward the results at said write-back stage to said decode stage.

15. A witchable conditional execution method performed in a very long instruction word (VLIW) processor, said method comprising the steps of

(a) arranging an instruction format for the VLIW processor to switch between two conditional modes, a conditional issue mode and a conditional write-back mode;

(b) performing different instruction scheduling schemas by the compiler for the VLIW processor according to different said conditional modes;

(c) the execution of a VLIW instruction being divided into a fetch stage, a decode stage, a plurality of execution stages, and a write-back stage; and

(d) for a conditional instruction, the conditional issue mode resolving the conditions for a conditional instruction at said decode stage, while said conditional write-back mode resolving the conditions the conditions for a conditional instruction at the last execution stage.

16. The switchable conditional execution method as claimed in claim 15, wherein in the step (a), said conditional issue mode is used to execute the conditional instructions when executing in a energy-saving mode, while said conditional write-back mode is used to execute the conditional instructions when executing in a high-performance mode.

17. The switchable conditional execution method as claimed in claim 15, wherein in the step (b), the scheduling schema under said conditional issue mode is an in-order-scheduling to arrange the execution time for each instruction, while the scheduling schema under said conditional write-back mode is an out-of-order-scheduling to arrange the pipeline behavior for each conditional instruction.