Method and apparatus for remotely buffering test channels

• US 7,453,258 B2
• Filed: 09/09/2004
• Issued: 11/18/2008
• Est. Priority Date: 09/09/2004
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A.
• Primary Examiner(s): Nguyen; Ha
• Assistant Examiner(s): Nguyen; Trung Q.
• Application Number:
  US10/937,470
• Publication Number:
  US 20060049820A1
• Time in Patent Office: 1,531 Days
• Field of Search: None
• US Class Current: 324/750.02
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test

Abstract

A system is provided to enable leakage current measurement or parametric tests to be performed with an isolation buffer provided in a channel line. Multiple such isolation buffers are used to connect a single signal channel to multiple lines. Leakage current measurement is provided by providing a buffer bypass element, such as a resistor or transmission gate, between the input and output of each buffer. The buffer bypass element can be used to calibrate buffer delay out of the test system by using TDR measurements to determine the buffer delay based on reflected pulses through the buffer bypass element. Buffer delay can likewise be calibrated out by comparing measurements of a buffered and non-buffered channel line, or by measuring a device having a known delay.

Claims

1. An apparatus comprising:

an isolation buffer provided in a test channel of a test system for testing an electronic device;

a buffer bypass element provided in the test channel between a signal input and output of the isolation buffer; and

a test probe configured to contact the electronic device,

wherein the test channel is configured to connect electrically at one end to a tester for controlling testing of the electronic device and terminates at another end in the test probe.

2. The apparatus of claim 1, wherein the buffer bypass element comprises a transmission gate.

3. The apparatus of claim 2, wherein the isolation buffer is a tristate buffer.

4. The apparatus of claim 1, wherein a signal is provided to disable the transmission gate when the tristate buffer is enabled and to enable the transmission gate when the tristate buffer is disabled.

5. The apparatus of claim 1, wherein the buffer bypass element comprises a transistor.

6. The apparatus of claim 5, wherein the transistor is a CMOS device having a source-drain path connected between the input and output of the isolation buffer.

7. The apparatus of claim 1, wherein the test channel comprises a common signal line electrically connected to a plurality of branch signal lines, the apparatus further comprising:

a plurality of test probes configured to contact a plurality of electronic devices to be tested, each branch terminating in one of the test probes;

a plurality of isolation buffers provided in each one of the branches; and

a plurality of buffer bypass elements each electrically connected in parallel with one of the isolation buffers.

8. The apparatus of claim 7 further comprising the tester, wherein the tester is configured to control testing of the electronic devices by providing test signals though the test channel to the electronic devices.

9. The apparatus of claim 7, wherein the test probes comprise resilient spring structures.

10. The apparatus of claim 1, wherein the buffer bypass element comprises a resistor.

11. A probe card comprising:

isolation buffers provided in test channels for testing electronic devices;

buffer bypass elements provided in parallel with the isolation buffers,

an electrical interface configured to electrically connect the test channels to a tester for controlling testing of the electronic devices; and

test probes configured to contact the electronic devices,

wherein the electrical interface is electrically connected to the test probes.

12. The probe card of claim 11, wherein the test channels are each terminated in one of the test probes.

13. The probe card of claim 12, wherein the test probes comprise resilient springs.

14. The apparatus of claim 11, wherein the buffer bypass elements comprise transmission gates.

15. The probe card of claim 11, wherein the test probes comprise resilient spring structures.

16. The probe card of claim 11, wherein at least one of the test channels comprises a common signal line electrically connected to a plurality of branch signal lines, and each branch signal line terminates in one of the probes.

17. The probe card of claim 16, wherein, in the at least one of the test channels, one of the isolation buffers is provided in each of the branch lines.

18. The probe card of claim 17, wherein, in the at least one of the test channels, each bypass element is connected to an input and an output of one of the isolation buffers.

19. The probe card of claim 17 further comprising an additional isolation buffer provided in the common signal line of the at least one of the test channels.

20. The probe card of claim 19, wherein, in the at least one of the test channels:

an output of the additional isolation buffer is connected to inputs of the isolation buffers; and

each bypass element is connected to an input of the additional isolation buffer and an output of one of the isolation buffers.

21. The apparatus of claim 11, wherein the buffer bypass elements comprise Resistor.

22. An apparatus comprising:

a signal line configured to connect electrically to a tester for testing electronic devices;

a plurality of branches from the signal line to a plurality of test probes configured to contact ones of the electronic devices;

isolation buffers, each isolation buffer provided in one of the branches; and

buffer bypass elements, each buffer bypass element electrically connected in parallel with one of the isolation buffers.

23. The apparatus of claim 22, further comprising an additional buffer provided in the signal line the additional buffer having an output connected to inputs of the isolation buffers, wherein each of the buffer bypass elements is electrically connected to an input of the additional buffer and an output of one of the isolation buffers.

24. The apparatus of claim 22, wherein the buffer bypass elements comprise transmission gates.

25. The apparatus of claim 24, wherein the additional buffer comprises a tristate buffer.

26. The apparatus of claim 25, wherein a signal is provided to disable the transmission gates when the tristate buffer is enabled and to enable the transmission gates when the tristate buffer is disabled.

27. The apparatus of claim 22, further comprising additional buffers, each additional buffer provided in series in with one of the isolation buffers in one of the branches, wherein the buffer bypass elements are provided in parallel with the series buffers in each branch.

28. The apparatus of claim 22, further comprising:

a delay control circuit having an output providing a variable delay control input to the isolation buffers, the delay control circuit setting a delay control voltage potential at its output to control delay through the isolation buffers to substantially match delay through a time delay reference.

29. The apparatus of claim 22, wherein each buffer bypass element is electrically connected to an input and an output of one of the isolation buffers.

30. The apparatus of claim 22, wherein the test probes comprise resilient spring structures.

31. The apparatus of claim 22, wherein the buffer bypass elements comprise resistors.