Ultra thin body fully-depleted SOI MOSFETs

• US 7,459,752 B2
• Filed: 06/23/2006
• Issued: 12/02/2008
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Min, Doris, Bruce B., Ren, Zhibin, Solomon, Paul M., Ieong, Meikei
• Primary Examiner(s): Purvis; Sue A.
• Assistant Examiner(s): Erdem; Fazli
• Application Number:
  US11/473,757
• Publication Number:
  US 20060237791A1
• Time in Patent Office: 893 Days
• Field of Search: 257/348, 257/347, 257/E21.445, 257/E21.444, 257/368, 257/369, 257/327, 257/E29.117, 257/E21.415
• US Class Current: 257/348
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Ultra thin body fully-depleted silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations are provided. Such a SOI MOSFET may include a SOI substrate having a SOI layer in which a first portion thereof has a thickness of less than 20 nm; a gate including a gate dielectric and a gate electrode located atop the first portion of the SOI layer having the thickness, the gate electrode having an upper surface and a bottom surface that have the same length or the bottom surface has a length that is greater than the upper surface; and source and drain diffusion regions located in a second portion of the SOI layer that is adjacent to the first portion, and the second portion of the SOI layer is thicker than the first portion.

Claims

1. A silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) comprising:

a silicon-on-insulator (SOI) substrate having a SOI layer in which a first portion thereof has a thickness of less than about 20 nm;

a gate including a gate dielectric and a gate electrode located atop the first portion of the SOI layer having said thickness, said gate electrode having an upper surface and a bottom surface that have the same length or said bottom surface has a length that is greater than the upper surface; and

source and drain diffusion regions located in a second portion of the SOI layer that is adjacent to said first portion, said second portion of the SOI layer is thicker than the first portion.

2. The SOI MOSFET of claim 1 further comprising an outer insulating spacer about the gate.

3. The SOI MOSFET of claim 1 wherein said gate conductor comprises doped polysilicon.

4. The SOI MOSFET of claim 1 further comprising an undoped or counter-doped device channel beneath said gate.

5. The SOI MOSFET of claim 1 further comprising a doped device channel beneath said gate.

6. The SOI MOSFET of claim 1 wherein said Si-containing layer is located on a surface of a buried oxide, said buried oxide having a thickness from about 100 nm to about 1000 nm.

7. A semiconductor structure comprising a plurality of fully-depleted metal oxide semiconductor field effect transistors (MOSFETs) located on a top Si-containing layer of a silicon-on-insulator substrate, wherein said top Si-containing layer under each MOSFET has a thickness that varies depending upon a gate length of each MOSFET, and each of said MOSFETS includes a gate electrode having an upper surface and a bottom surface that have the same length or said bottom surface has a length that is greater than the upper surface.

8. The semiconductor structure of claim 7 wherein each MOSFET comprises:

a device channel in said top Si-containing layer having a vertical thickness of less than about 20 nm;

a gate including a gate dielectric and said gate electrode located atop the device channel; and

source and drain diffusion regions located in said top Si-containing layer that is adjacent to said device channel, said top Si-containing layer adjacent to said device channel is thicker than the device channel.

9. The semiconductor structure of claim 8 further comprising an outer insulating spacer about the gate.

10. The semiconductor structure of claim 8 wherein said gate conductor comprises doped polysilicon.

11. The semiconductor structure of claim 7 wherein said some of said device channels are undoped or counter-doped.

12. The semiconductor structure of claim 7 wherein some of device channels are doped.

13. The semiconductor structure of claim 7 wherein said device channels of some of said pluralarity of MOSFET are undoped or counterdoped and the device channel of the other MOSFETs are doped.

14. The semiconductor structure of claim 7 wherein said top Si-containing layer is located on a surface of a buried oxide, said buried oxide having a thickness from about 100 nm to about 1000 nm.

15. A silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) comprising:

a silicon-on-insulator (SOI) substrate having a SOI layer in which a first portion thereof has a thickness of less than about 20 nm, said SOI layer is located on a surface of a buried oxide having a thickness from 100 nm to about 1000 nm;

a gate including a gate dielectric and a gate electrode located atop the first portion of the SOI layer having said thickness, said gate electrode having an upper surface and a bottom surface that have the same length or said bottom surface has a length that is greater than the upper surface;

source and drain diffusion regions located in a second portion of the SOI layer that is adjacent to said first portion, said second portion of the SOI layer is thicker than the first portion; and

an outer insulating spacer about the gate, said outer insulating spacer having an upper surface portion that is coplanar to the upper surface of said gate electrode, and is spaced apart from a vertical sidewall of said gate electrode by said gate dielectric.

16. The SOI MOSFET of claim 15 wherein said gate conductor comprises doped polysilicon.

17. The SOI MOSFET of claim 15 further comprising an undoped or counter-doped device channel beneath said gate.

18. The SOI MOSPET of claim 15 further comprising a doped device channel beneath said gate.