Equalization and decision-directed loops with trellis demodulation in high definition TV

• US 7,474,695 B2
• Filed: 07/21/2004
• Issued: 01/06/2009
• Est. Priority Date: 11/03/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Tan, Loke Kun, Liu, Tian-Min, Jaffe, Steven T.
• Primary Examiner(s): Corrielus; Jean B
• Application Number:
  US10/895,879
• Publication Number:
  US 20040258184A1
• Time in Patent Office: 1,630 Days
• Field of Search: 375229-234, 375/346, 375/348, 375/350, 375320-321, 375/324, 375/340, 375269-270, 329/304
• US Class Current: 375/233
• CPC Class Codes: H04B 1/68 for wholly or partially suppressing the carrier or one side band
• CPC Class Codes: H04L 2025/03382 Single of vestigal sideband
• CPC Class Codes: H04L 2025/0342 QAM
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2027/0032 at baseband and passband
• CPC Class Codes: H04L 2027/0042 the equaliser providing the offset correction per se
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0087 Out-of-band signals, (e.g. pilots)
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/066 Carrier recovery circuits H04L27/2271 takes precedence
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 27/3427 in which the constellation is the n - fold Cartesian product of a single underlying two-dimensional constellation
• CPC Class Codes: H04L 27/3827 in which the carrier is recovered using only the demodulated baseband signals
• CPC Class Codes: H04N 11/24 High-definition television systems
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
• CPC Class Codes: H04N 5/211 Ghost signal cancellation H04N23/81 takes precedence
• CPC Class Codes: H04N 5/44 : Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27

Abstract

Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE'"'"'s ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

Claims

1. A method for equalizing a first complex quadrature amplitude modulated (QAM) signal, comprising:

applying a second complex QAM signal to a first decision device;

combining the second complex QAM signal and the output of the first decision device to produce a complex error term;

applying the complex error term to a single tap derotator to produce a correction term;

applying the first complex QAM signal and the correction term to a multiplier to produce the second complex QAM signal;

applying the second complex QAM signal to a feed forward equalizer (FFE);

combining an output of the FFE and a timing reference signal to produce a timed signal;

combining the timed signal and an output of a decision feedback equalizer (DFE) to produce a summed signal;

applying the summed signal to a second decision device;

applying an output of the second decision device to the DFE;

combining the summed signal with the output of the second decision device to produce an error signal;

applying the error signal to a QAM phase detector or a VSB phase detector based on a modulation of the first complex QAM; and

generating the timing reference signal based on an output of the QAM phase detector or an output of the VSB phase detector.

2. The method of claim 1,

wherein the DFE has adjustable taps, the method further comprising:

adjusting the taps of the DFE responsive to the second complex QAM signal.

3. The method of claim 2, further comprising:

recovering data embedded in the first complex QAM signal, the method additionally comprising adjusting a timing loop responsive to the first complex QAM signal.

4. The method of claim 3, further comprising:

adjusting a carrier loop responsive to the first complex QAM signal to derotate the first complex QAM signal.

5. The method of claim 1,

wherein the DFE has adjustable taps, the method further comprising:

adjusting the taps of the DFE responsive to the first complex QAM signal.

6. The method of claim 1, further comprising:

recovering data embedded in the first complex QAM signal, the method additionally comprising adjusting a timing loop responsive to the first complex QAM signal.

7. The method of claim 1, further comprising:

adjusting a carrier loop responsive to the first complex QAM signal to derotate the first complex QAM signal.

8. The method of claim 1, further comprising:

filtering the output of the QAM phase detector or the output of the VSB phase detector to produce a control signal.

9. The method of claim 8, wherein the step of filtering the output of the QAM phase detector or the output of the VSB phase detector comprises:

filtering the output of the QAM phase detector or the output of the VSB phase detector to produce the control signal for a timing reference circuit.

10. The method of claim 8, further comprising:

generating the timing reference signal based on the control signal.

11. The method of claim 1, wherein the step of generating the timing reference signal comprises:

generating the timing reference signal using a numerically controlled oscillator (NCO) a voltage controlled oscillator (VCO) or a direct digital frequency synthesizer (DDDFS).