Method and apparatus to reduce latency and improve throughput of input/output data in a processor
First Claim
Patent Images
1. A method comprising:
- receiving a first portion and a second portion of at least one packet at an input/output device; and
transferring the first portion between a register circuit of a processor and the input/output device without transferring the first portion to a memory device coupled to the processor; and
transferring the second portion between a cache memory circuit of the processor and the input/output device without transferring the second portion to the memory device.
3 Assignments
0 Petitions
Accused Products
Abstract
Some embodiments include apparatus and method having a register circuit to receive a first portion of a packet from an input/output device, cache memory circuit to receive a second portion of the package, and a processing unit to process at least one of the first and second portions of the packet based on instructions in the processing unit. The processing unit and the register circuit reside on a processor. The first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor. The second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.
-
Citations
20 Claims
-
1. A method comprising:
-
receiving a first portion and a second portion of at least one packet at an input/output device; and transferring the first portion between a register circuit of a processor and the input/output device without transferring the first portion to a memory device coupled to the processor; and transferring the second portion between a cache memory circuit of the processor and the input/output device without transferring the second portion to the memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. An apparatus comprising:
-
a register circuit to receive a first portion of a packet from an input/output device; a cache memory circuit to receive a second portion of the packet; and a processing unit to process the first and second portions of the packet based on instructions in the processing unit, the processing unit and the register circuit residing on a processor, wherein the first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor, and wherein the second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
-
-
16. An article including a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:
-
receiving a first portion and a second portion of at least one packet at an input/output device; and transferring the first portion between a register circuit of a processor and the input/output device without transferring the first portion to a memory device coupled to the processor; and transferring the second portion between a cache memory circuit of the processor and the input/output device without transferring the second portion to the memory device. - View Dependent Claims (17, 18, 19, 20)
-
Specification