Method and apparatus to reduce latency and improve throughput of input/output data in a processor

• US 7,480,747 B2
• Filed: 06/08/2005
• Issued: 01/20/2009
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Bell, D. Michael, Vasudevan, Anil
• Primary Examiner(s): Tsai; Henry H. W.
• Assistant Examiner(s): TSENG, CHENG YUAN
• Application Number:
  US11/147,991
• Publication Number:
  US 20060282560A1
• Time in Patent Office: 1,322 Days
• Field of Search: 710/33, 710/1, 710/65, 710/105, 710/22, 709/226, 709/232, 709/249, 709/250, 709/230, 709/231, 709/236, 709/238, 709/239, 709/240, 709/243, 709/245, 718/100, 718/102, 370/465, 370/474, 370/389, 370/392, 370/395, 370/412, 370/419, 209/218, 711/135
• US Class Current: 710/33
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

Some embodiments include apparatus and method having a register circuit to receive a first portion of a packet from an input/output device, cache memory circuit to receive a second portion of the package, and a processing unit to process at least one of the first and second portions of the packet based on instructions in the processing unit. The processing unit and the register circuit reside on a processor. The first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor. The second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.

Claims

1. A method comprising:

receiving a first portion and a second portion of at least one packet at an input/output device; and

transferring the first portion between a register circuit of a processor and the input/output device without transferring the first portion to a memory device coupled to the processor; and

transferring the second portion between a cache memory circuit of the processor and the input/output device without transferring the second portion to the memory device.

2. The method of claim 1, wherein transferring one of the first and second portions is performed without accessing the cache memory circuit of the processor to search for information associated with the packet.

3. The method of claim 2, wherein the processor processes the first and second portions without receiving from the input/output device an interrupt request associated with the packet.

4. The method of claim 1, wherein the first portion includes a header of the packet.

5. The method of claim 4, wherein the second portion includes a payload of the packet.

6. The method of claim 1, wherein the packet is complied with TCP/IP (Transport Control Protocol/Internet Protocol).

7. The method of claim 1 further comprising:

transferring between the register circuit of the processor and the input/output device a packet descriptor associated with the packet without transferring the packet descriptor to the memory device.

8. An apparatus comprising:

a register circuit to receive a first portion of a packet from an input/output device;

a cache memory circuit to receive a second portion of the packet; and

a processing unit to process the first and second portions of the packet based on instructions in the processing unit, the processing unit and the register circuit residing on a processor, wherein the first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor, and wherein the second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.

9. The apparatus of claim 8, wherein the processing unit is configured to process the first portion of the packet without searching the cache memory circuit for information associated with the packet.

10. The apparatus of claim 9, wherein the processing unit is configured to process the first and second portions of the packet without receiving from the input/output device an interrupt request associated with the packet.

11. The apparatus of claim 8, wherein the register circuit is configured to receive a header of the package and the cache memory circuit is configured to receive a payload of the packet, and wherein the second portion of the package includes the payload and the first portion of the packet includes the header.

12. The apparatus of claim 11, wherein the register circuit is configured to send at least one outgoing packet directly to the input/output device, bypassing the memory device.

13. The apparatus of claim 8, wherein the cache memory circuit is configured to send at least one outgoing payload directly to the input/output device, bypassing the memory device.

14. The apparatus of claim 8, wherein the processor includes a number of terminals to connect the processor directly to the input/output device via a connection to allow the processor to communicate directly with the input/output device via the connection.

15. The apparatus of claim 8, wherein the processor includes a number of terminals to indirectly connect the processor to the input/output device via a shared interconnection.

16. An article including a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:

receiving a first portion and a second portion of at least one packet at an input/output device; and

transferring the first portion between a register circuit of a processor and the input/output device without transferring the first portion to a memory device coupled to the processor; and

transferring the second portion between a cache memory circuit of the processor and the input/output device without transferring the second portion to the memory device.

17. The article of claim 16, wherein transferring one of the first and second portions is performed without accessing the cache memory circuit of the processor to search for information associated with the packet.

18. The article of claim 17, wherein the processor processes the first and second portions without receiving from the input/output device an interrupt request associated with the packet.

19. The article of claim 16, wherein the first portion includes a header of the packet.

20. The article of claim 19, wherein the second portion includes a payload of the packet.