Electronic device and method of manufacturing the same
First Claim
Patent Images
1. A ferroelectric random access memory (FRAM), comprising:
- a lower PRAM includinga first substrate;
a first lower capacitor on the first substrate;
a first lower switching element on the first lower capacitor;
a second substrate on the first lower switching element;
a first bit line on the second substrate of the lower FRAM, the first bit line being connected to the first lower switching element of the lower FRAM; and
an upper FRAM on the second substrate of the lower FRAM, the upper FRAM including a first upper capacitor having a lower electrode spaced apart from the first bit line and a first upper switching element on the first upper capacitor.
1 Assignment
0 Petitions
Accused Products
Abstract
In an electronic device, and a method of manufacturing the same, the electronic device includes a first substrate, a first lower capacitor on the first substrate, a first lower switching element on the first lower capacitor, and a second substrate on the first lower switching element. The electronic device may further include a second lower switching element which is isolated from the first lower capacitor, and an upper capacitor on the second substrate, the lower electrode of the upper capacitor being connected to the second lower switching element.
10 Citations
56 Claims
-
1. A ferroelectric random access memory (FRAM), comprising:
-
a lower PRAM including a first substrate; a first lower capacitor on the first substrate; a first lower switching element on the first lower capacitor; a second substrate on the first lower switching element; a first bit line on the second substrate of the lower FRAM, the first bit line being connected to the first lower switching element of the lower FRAM; and an upper FRAM on the second substrate of the lower FRAM, the upper FRAM including a first upper capacitor having a lower electrode spaced apart from the first bit line and a first upper switching element on the first upper capacitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. A ferroelectric random access memory (FRAM), comprising:
-
a first substrate; a first lower capacitor on the first substrate; a first lower switching element on the first lower capacitor; a second substrate on the first lower switching element; a second lower switching element between the first substrate and the second substrate; a first bit line on the second substrate, the first bit line being connected to the first lower switching element; and an upper capacitor on the second substrate, the upper capacitor including a lower electrode that is isolated from the first bit line and is connected to the second lower switching element and the second substrate being disposed between the upper capacitor and the first lower capacitor. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
-
-
34. A method of manufacturing a ferroelectric random access memory (FRAM), comprising:
-
(a) forming a first capacitor on a first surface of a first substrate; (b) forming a first switching element on a first surface of a second substrate; (c) bonding the first capacitor to the first switching element; (d) forming a first bit line on a second surface of the second substrate, the first bit line being connected to the first switching element; and (e) forming an FRAM layer on the second surface of the second substrate such that the second substrate is between the first capacitor and the FRAM layer, the FRAM layer including an upper capacitor having a lower electrode spaced apart from the first bit line and an upper switching element on the upper capacitor. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
-
-
49. A method of manufacturing a ferroelectric random access memory (FRAM), comprising:
-
(a) forming a first capacitor on a first surface of a first substrate; (b) forming a first switching element on a first surface of a second substrate; (c) bonding the first capacitor to the first switching element; (d) forming a second switching element between the first substrate and the second (e) forming a first bit line on a second surface of the second substrate, the first bit line being connected to the first switching element; and (f) forming an upper capacitor on the second surface of the second substrate such that the second substrate is between the upper capacitor and the first capacitor, the upper capacitor including a lower electrode that is isolated from the bit line and is connected to the second switching element. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56)
-
Specification