High performance IP processor

• US 7,487,264 B2
• Filed: 06/10/2003
• Issued: 02/03/2009
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Memory Access Technologies LLC
• Original Assignee: Ashish A. Pandya
• Inventors: Pandya, Ashish A.
• Primary Examiner(s): Donaghue, Larry D
• Application Number:
  US10/459,297
• Publication Number:
  US 20040030757A1
• Time in Patent Office: 2,065 Days
• Field of Search: 709/250
• US Class Current: 709/250
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol Layer and may also provide packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.

Claims

1. An Internet Protocol (IP) processor system for enabling Transmission Control Protocol (TCP) or Stream Control Transmission Protocol (SCTP), or User Datagram Protocol (UDP), or other session oriented protocols over IP networks, said IP processor system comprising:

a. a plurality of packet processors for processing a plurality of packets including a first packet and a second packet, wherein the first packet and the second packet each have a connection ID associated therewith;

b. a session memory for storing IP session information related to the packets;

c. at least one memory controller for controlling memory accesses, wherein the memory accesses are performed to obtain session information of the packets;

d. at least one media interface for coupling to at least one network, wherein the packets are communicated via the at least one network;

e. a host interface configured to communicate a command to said IP processor system, and coupled to at least one host or a fabric interface coupled to a fabric; and

f. a scheduler configured to assign the first packet to one of the packet processors executing the second packet based on at least the connection ID associated with each of the first packet and the second packet.

2. The IP processor system of claim 1 further comprising at least one of:

a. an IP Storage session memory for storing IP Storage session information;

b. a classification processor for classifying the packets;

c. a flow controller for controlling data flow;

d. a policy processor for applying policies;

e. a security processor for performing security operations;

f. a packet memory for storing the packets;

g. a controller for control plane processing;

h. a packet scheduler;

i. a connection manager or session controller for managing sessions;

or

j. a combination of any of the foregoing.

3. The IP processor system of claim 1, wherein said packet processors are configured to be scaled based on a line rate of the at least one network.

4. The IP processor system of claim 1, wherein said IP processor system is coupled to said at least one host, and said packet processors are configured to offload a process from said at least one host.

5. The IP processor system of claim 1, wherein said packet processors are located on the same chip.

6. A hardware implemented Internet Protocol (IP) network application processor for providing Transmission Control Protocol/Internet Protocol (TCP/IP) operations in sessions on a plurality of information packets transported between an initiator computer system and a target computer system, said hardware implemented IP network application processor comprising:

a. a plurality of data processing resources including at least one programmable packet processor for processing said packets;

b. a TCP/IP session cache and memory controller configured to track progress of and configured to control a memory useful in the processing performed on said packets;

c. a host interface controller capable of controlling an interface to a host processor in the initiator computer system or the target computer system or a fabric interface controller capable of controlling an interface to a fabric; and

d. a media independent interface capable of controlling an interface to a network media in the initiator computer system or the target computer system.

7. An Internet Protocol (IP) processor system for enabling Transmission Control Protocol (TCP) or other session oriented protocols over IP networks, said IP processor system comprising:

a. at least one packet processor for processing a plurality of packets including a first packet and a second packet;

b. a session memory for storing IP session information related to the packets;

c. at least one memory controller for controlling memory accesses, wherein the memory accesses are performed to obtain session information of the packets;

d. at least one media interface for coupling to at least one network, wherein the packets are communicated via the at least one network; and

e. a host interface configured to communicate a command to said IP processor system, and coupled to at least one host or a fabric interface coupled to a fabric;

i. wherein said IP processor system operates in multiple stages including at least two of (1) receiving the packets;

(2) providing security for the packets;

(3) classifying the packets;

(4) scheduling the packets for processing, wherein the second packet is executed on one of the packet processors and the first packet is executed on the packet processor executing the second packet based on a connection ID associated with each of the first packet and the second packet;

(5) executing data processing operations on the packets;

(6) providing direct memory access for transferring the packets to or from a memory of a system external to said IP processor system;

(7) transmitting the packets onto the at least one network;

(8) executing packet processing operations on data or commands forming the packets; and

(9) providing security for the packets, and

(a) wherein a first stage of the at least two stages is configured to operate on the first packet concurrently with an operation performed by a second one of the at least two stages on the second packet.

8. A Transmission Control Protocol (TCP)/Internet Protocol (IP) (TCP/IP) processor system for enabling TCP, Stream Control Transmission Protocol (SCTP), or User Datagram Protocol (UDP) or other session oriented protocols, over IP networks, said TCP/IP processor system comprising:

a. a plurality of packet processor engines for processing a plurality of packets including a first packet and a second packet, wherein one of the packet processor engines comprises a TCP/IP processor engine configured to execute a TCP/IP protocol on the packets and wherein the first packet and the second packet each have a connection ID associated therewith;

b. a session memory for storing session information related to the packets;

c. at least one memory controller for controlling memory accesses, wherein the memory accesses are performed to obtain session information of the packets;

d. at least one media interface for coupling to at least one network, wherein the packets are communicated via the at least one network;

e. a host interface configured to communicate a command to said TCP/IP processor system, and coupled to at least one host or a fabric interface coupled to a fabric; and

f. a scheduler configured to assign the first packet to the one of the packet processor engines executing the second packet based on at least the connection ID associated with each of the first packet and the second packet.

9. The TCP/IP processor system of claim 8 further comprising at least one of:

a. a classification processor for classifying the packets;

b. a flow controller for controlling data flow;

c. a policy processor for applying policies;

d. a security processor for performing security operations;

e. a controller for control plane processing;

f. a packet scheduler;

g. a packet memory for storing the packets;

h. a connection manager or session controller for managing sessions;

or

i. a combination of any of the foregoing.

10. An Internet Protocol (IP) Storage processor system for enabling IP Storage protocols over IP networks, said IP Storage processor system comprising:

a. a plurality of packet processor engines configured to process a plurality of storage packets including a first storage packet and a second storage packet, wherein said packet processor engines comprise at least one IP Storage processor engine for applying an Internet Protocol to the storage packets, wherein the first storage packet and the second storage packet each have a connection ID associated therewith;

b. an IP Storage session memory for storing session information related to the storage packets;

c. at least one memory controller for controlling memory accesses, wherein the memory accesses are performed to obtain session information of the storage packets;

d. at least one media interface for coupling to at least one network, wherein the storage packets are communicated via the at least one network;

e. a host interface configured to communicate a command to said IP Storage processor, and coupled to at least one host or a fabric interface coupled to a fabric; and

f. a scheduler configured to assign the first storage packet to one of the packet processor engines executing the second packet based on at least the connection ID associated with each of the first storage packet and the second storage packet.

11. The IP Storage processor system of claim 10 further comprising at least one of:

a. a classification processor for classifying the packets;

b. a flow controller for controlling data flow;

c. a policy processor for applying policies;

d. a security processor for performing security operations;

e. a controller for control plane processing;

f. a packet scheduler;

g. a packet memory for storing the packets;

or

h. a combination of any of the foregoing.

12. An Internet protocol (IP) processor system for enabling TCP or other session oriented protocols over IP networks, said IP processor system comprising:

a. at least one packet processor for processing a plurality of packets including a first packet and a second packet, wherein the first packet and the second packet each have a connection ID associated therewith;

b. a session memory for storing IP session information related to the packets;

c. at least one memory controller for controlling memory accesses, wherein the memory accesses are performed to obtain session information of the packets;

d. at least one media interface for coupling to at least one network, wherein the packets are communicated via the at least one network;

e. a host interface configured to communicate a command to said IP processor system, and coupled to at least one host or a fabric interface coupled to a fabric; and

i. wherein said IP processor system operates in multiple stages including at least two of (1) receiving the packets;

(2) providing security for processing the packets if needed;

(3) classifying the packets;

(4) scheduling the packets for processing, wherein the second packet is executed on one of the packet processors and the first packet is executed on the packet processor executing the second packet based on a connection ID associated with each of the first packet and the second packet;

(5) executing data and/or processing operations on the packets;

(6) providing direct memory access for transferring the packets to or from a memory of a system external to said IP processor system;

(7) executing protocol processing operations on data or commands forming the packets;

(8) providing processing security for the packets, if needed; and

(9) transmitting the packets onto the at least one network; and

ii. wherein a first stage of the at least two stages is configured to operate on the first packet concurrently with an operation performed by a second one of the at least two stages on the second packet.

13. The IP processor system of claim 12, wherein each stage of said IP processor system may take a different length of time to perform its function than one or more of the other stages of said IP processor system.

14. A Transmission Control Protocol (TCP)/Internet Protocol (IP) (TCP/IP) processor system for enabling TCP over IP networks, said TCP/IP processor system including a TCP/IP stack providing TCP/IP protocol termination and origination, said TCP/IP processor system comprising:

a. A plurality of packet processor engines for processing a plurality of packets including a first packet and a second packet, wherein the first packet and the second packet each have a connection ID herewith, wherein one of the packet processor engines comprises a TCP/IP processor engine configured to execute a TCP/IP protocol on the packets;

b. A session memory for storing session information related to the packets;

c. At least one memory controller for controlling memory accesses, wherein the memory accesses are performed to obtain session information of the packets;

d. At least one media interface for coupling to at least one network, wherein the packets are communicated via the at least one network, wherein said packet processor engines are configured to be scaled based on a line rate of the at least one network;

e. A host interface configured to communicate a command to said IP processor, and coupled to at least one host or a fabric interface coupled to a fabric; and

f. A scheduler configured to assign the first packet to one of the packet processor engines executing the second packet based on at least the connection ID associated with each of the first packet and the second packet.

15. The TCP/IP processor system of claim 14 further comprising at least one of:

a. a classification processor for classifying the packets;

b. a flow controller for controlling data flow;

c. a policy processor for applying policies;

d. a security processor for performing security operations;

e. a controller for control plane processing;

f. a packet scheduler for scheduling the packets;

g. a packet memory for storing the packets;

h. a connection manager or session controller for managing TCP/IP sessions;

or

i. a combination of any of the foregoing.

20. The TCP/IP processor system of claim 14 wherein said TCP/IP processor system operates in multiple stages, including one or more stages of:

a. Receiving the packets;

b. Providing security processing for the packets if necessary;

c. Classifying the packets;

d. Scheduling the packets for processing;

e. Executing data and/or protocol processing operations on the packets;

f. Providing direct memory access for transferring data/packets to or from a memory of a system external to said TCP/IP processor system;

g. Executing protocol processing operations on data or commands forming the packets;

h. Providing security processing for the packets if necessary;

i. Transmitting the packets onto the at least one network;

or

j. A combination of any of the foregoing; and

i. Each of said stages is capable of operating on different IP packets concurrently.

16. A Transmission Control Protocol (TCP)/Internet Protocol (IP) (TCP/IP) processor system for enabling TCP over IP networks, said TCP/IP processor system including a TCP/IP stack providing TCP/IP protocol termination and origination, said stack providing an interface to sockets layer functions in a host processor to transport data traffic, said TCP/IP processor system comprising:

a. A plurality of packet processor engines for processing a plurality of packets including a first packet and a second packet, wherein one of the packet processor engines comprises a TCP/IP processor engine configured to execute a TCP/IP protocol on the packets, wherein said packet processor engines are located on the same chip, wherein the first packet and the second packet each have a connection ID associated therewith;

b. A session memory for storing session information related to the packets;

c. At least one memory controller for controlling memory accesses, wherein the memory accesses are performed to obtain session information of the packets;

d. At least one media interface for coupling to at least one network, wherein the packets are communicated via the at least one network;

e. A host interface configured to communicate a command to said IP processor, and coupled to at least one host or a fabric interface coupled to a fabric; and

f. A scheduler configured to assign the first packet to one of the packet processor engines executing the second packet based on at least the connection ID associated with each of the first packet and the second packet.

17. The TCP/IP processor system of claim 16 further comprising at least one of:

a. a classification processor for classifying the packets;

b. a flow controller for controlling data flow;

c. a policy processor for applying policies;

d. a security processor for performing security operations;

e. a controller for control plane processing;

f. a packet scheduler for scheduling the packets;

g. a packet memory for storing the packets;

h. a connection manager or session controller for managing TCP/IP sessions;

or

i. a combination of any of the foregoing.

21. The TCP/IP processor system of claim 16 wherein said TCP/IP processor system operates in multiple stages, including one or more stages of

a. Receiving the packets;

b. Providing security processing for the packets if necessary;

c. Classifying the packets;

d. Scheduling the packets for processing;

e. Executing data and/or protocol processing operations on the packets;

f. Providing direct memory access for transferring the packets to or from the memory of a system external to said TCP/IP processor system;

g. Executing protocol processing operations on data or commands forming the packets;

h. Providing security processing for the packets if necessary;

i. Transmitting the packets onto the at least one network;

or

j. A combination of any of the foregoing; and

i. Each of said stages is capable of operating on different IP packets concurrently.

18. An Internet Protocol (IP) Storage processor system for enabling IP Storage protocols over IP networks, said IP Storage processor system including an IP Storage stack providing IP Storage protocol termination and origination, transporting information in active sessions over IP networks by transporting Protocol Data Units (PDU'"'"'s) specified by the IP storage standard, said IP processor system comprising:

a. A plurality of packet processor engines for processing a plurality of packets, wherein one of said packet processor engines includes an IP Storage processor engine configured to apply an Internet Small Computer System Interface (iSCSI) protocol to the packets, wherein said packet processor engines including a first storage packet and a second storage packet, wherein the first packet and the second packet each have a connection ID associated therewith;

b. An IP Storage session memory for storing session information related to the packets;

c. At least one memory controller for controlling memory accesses, wherein the memory accesses are performed to obtain session information of the packets;

d. At least one media interface for coupling to at least one network, wherein the packets are communicated via the at least one network;

e. A host interface configured to communicate a command to said IP Storage processor, and coupled to at least one host or a fabric interface coupled to a fabric; and

f. A scheduler configured to assign the first packet to one of the packet processor engines executing the second packet based on at least the connection ID associated with each of the first packet and the second packet.

19. The IP Storage processor system of claim 18 further comprising at least one of:

a. A classification processor for classifying the packets;

b. a flow controller for controlling data flow;

c. a policy processor for applying policies;

d. a security processor for performing security operations;

e. a controller for control plane processing;

f. a packet scheduler for scheduling the packets;

g. a packet memory for storing the packets;

or,

h. a combination of any of the foregoing.

22. The IP Storage processor system of claim 18 wherein said processor operates in multiple stages, including one or more stages of

a. Receiving the packets;

b. Providing security processing for the packets if necessary;

c. Classifying the packets;

d. Scheduling the packets for processing;

e. Executing data and/or protocol processing operations on the packets;

f. Providing direct memory access for transferring the packets to or from the memory of a system external to said IP Storage processor system;

g. Executing protocol processing operations on data or commands forming the packets;

h. Providing security processing for the packets if necessary;

i. Transmitting the packets onto the at least one network;

or

j. A combination of any of the foregoing; and

i. Each of said stages is capable of operating on different IP packets concurrently.