Memory utilizing oxide-nitride nanolaminates

• US 7,489,545 B2
• Filed: 07/25/2006
• Issued: 02/10/2009
• Est. Priority Date: 07/08/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/492,749
• Publication Number:
  US 20060258097A1
• Time in Patent Office: 931 Days
• Field of Search: 365/185.05, 365/185.03, 365/185.02, 365/210, 365/51, 365/63, 257/327, 257/325, 257/760
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Claims

1. A method for operating a memory, comprising:

writing to one or more vertical MOSFETs arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the DRAM array includes a number of sourcelines formed in a bottom of the trenches between rows of the vertical MOSFETs and coupled to the source regions of each transistor along rows the vertical MOSFETs, wherein along columns of the vertical MOSFETs the source region of each column adjacent vertical MOSFET couple to the sourceline in a shared trench, and wherein the DRAM array includes a number of bitlines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical MOSFETs in the reverse direction includes;

biasing a sourceline for two column adjacent vertical MOSFETs sharing a trench to a voltage higher than VDD;

grounding a bitline coupled to one of the drain regions of the two column adjacent vertical MOSFETs in the vertical MOSFET to be programmed;

applying a gate potential to the gate for each of the two column adjacent vertical MOSFETs to create a hot electron injection into the gate insulator of the vertical MOSFET to be programmed adjacent to the source region such that an addressed MOSFET becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction;

reading one or more vertical MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes;

grounding a sourceline for two column adjacent vertical MOSFETs sharing a trench;

precharging the drain regions of the two column adjacent vertical MOSFETs sharing a trench to a fractional voltage of VDD;

applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical MOSFETs sharing a trench such that a conductivity state of an addressed vertical MOSFET can be compared to a conductivity state of a reference cell; and

wherein storing the charge within the storage layer less than or equal to 10 nanometers thick includes storing a charge within a storage layer approximately 4 nanometers thick.

2. The method of claim 1, wherein creating a hot electron injection into the gate insulator of the addressed MOSFET adjacent to the source region includes creating a first threshold voltage region (Vt1) adjacent to the drain region and creating a second threshold voltage region (Vt2) adjacent to the source region, wherein Vt2 is greater that Vt1.

3. The method of claim 1, wherein reading one or more vertical MOSFETs in the DRAM array in a forward direction includes using a sense amplifier to detect whether an addressed vertical MOSFET is a programmed vertical MOSFET, wherein a programmed vertical MOSFET will not conduct, and wherein an un-programmed vertical MOSFET addressed over approximately 10 ns will conduct a current of approximately 12.5 μ

A such that the method includes detecting an integrated drain current having a charge of 800,000 electrons using the sense amplifier.

4. The method of claim 1, wherein in creating a hot electron injection into the gate insulator of an addressed vertical MOSFET includes changing a threshold voltage for the vertical MOSFET by approximately 0.5 Volts.

5. The method of claim 1, wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 10¹² electrons/cm².

6. The method of claim 1, wherein creating a hot electron injection into the gate insulator of the addressed vertical MOSFET includes trapping a stored charge in the gate insulator of the addressed vertical MOSFET of approximately 100 electrons.

7. The method of claim 1, wherein the method further includes using the vertical MOSFET as active device with gain, and wherein reading a programmed vertical MOSFET includes providing an amplification of a stored charge in the gate insulator from 100 to 800,000 electrons over a read address period of approximately 10 ns.

8. A method of operating a memory array, comprising:

writing a memory state to at least one of a plurality of vertical transistors in an array, including;

storing a charge within a storage layer of a nanolaminate insulator, wherein the storage layer is formed using atomic layer deposition techniques, and the nanolaminate insulator is located on a trench wall, and wherein the nanolaminate insulator layer separates a channel region within the trench wall from a gate located over the nanolaminate insulator within the trench;

wherein storing the charge is performed in a first direction;

reading the memory state of the vertical transistor in a second direction opposite from the first direction; and

further including comparing a source/drain current in the vertical transistor a reference source/drain current in a second vertical transistor.

9. The method of claim 8, wherein comparing the source/drain current to the reference source/drain current includes comparing to a reference source/drain current in a second vertical transistor located on an adjacent wall of the trench.

10. The method of claim 8, wherein storing the charge within the storage layer of a nanolaminate insulator includes storing a charge within a storage layer less than or equal to 10 nanometers thick.

11. A method of operating a memory array, comprising:

writing a memory state to at least one of a plurality of vertical transistors in an array, including;

storing a charge within a storage layer of a nanolaminate insulator, wherein the storage layer is formed using atomic layer deposition techniques, and the nanolaminate insulator is located on a trench wall, and wherein the nanolaminate insulator layer separates a channel region within the trench wall from a gate located over the nanolaminate insulator within the trench;

wherein storing the charge is performed in a first direction; and

reading the memory state of the vertical transistor in a second direction opposite from the first direction, including comparing a source/drain current of the vertical transistor in the second direction with source/drain current of a vertical reference transistor on an adjacent side of the trench.

12. The method of claim 11, wherein comparing a source/drain current of the vertical transistor in the second direction with source/drain current of a vertical reference transistor includes utilizing a common source line buried in a base of the trench.

13. The method of claim 11, wherein comparing a source/drain current of the vertical transistor in the second direction with source/drain current of a vertical reference transistor includes utilizing a gate that is shared between the vertical transistor and the reference vertical transistor.

14. The method of claim 11, wherein storing the charge within the storage layer of a nanolaminate insulator includes storing a charge within a storage layer less than or equal to 10 nanometers thick.

15. The method of claim 14, wherein storing the charge within the storage layer less than or equal to 10 nanometers thick includes storing a charge within a storage layer approximately 4 nanometers thick.

16. A method of operating a memory array, comprising:

writing a memory state to at least one of a plurality of vertical transistors in an array, including;

storing a charge within a nitride storage layer of a nanolaminate insulator, wherein the nitride storage layer is formed using atomic layer deposition techniques, and the nanolaminate insulator is located on a trench wall, and wherein the nanolaminate insulator layer separates a channel region within the trench wall from a gate located over the nanolaminate insulator within the trench;

wherein storing the charge is performed in a first direction;

reading the memory state of the vertical transistor in a second direction opposite from the first direction; and

wherein storing a charge within a nitride storage layer includes storing a charge within a Storage layer with an electron affinity less than 4.1 eV providing a positive conduction band offset with silicon oxide.

17. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a silicon nitride storage layer.

18. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within an aluminum nitride storage layer.

19. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a gallium nitride storage layer.

20. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a gallium aluminum nitride storage layer.

21. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a tantalum aluminum nitride storage layer.

22. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a titanium silicon nitride storage layer.

23. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a titanium aluminum nitride storage layer.

24. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a tungsten aluminum nitride storage layer.