Non-volatile memory device with a select gate electrode and a control gate electrode formed on a floating gate

• US 7,492,002 B2
• Filed: 12/30/2005
• Issued: 02/17/2009
• Est. Priority Date: 12/30/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yong-Tae, Han, Jeong-Uk, Jeon, Hee-Seog, Yoon, Seung-Beom
• Primary Examiner(s): Nguyen; Tuan T
• Assistant Examiner(s): Bernstein; Allison P
• Application Number:
  US11/323,355
• Publication Number:
  US 20060170028A1
• Time in Patent Office: 1,145 Days
• Field of Search: 257314-316, 257319-321
• US Class Current: 257/321
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

Claims

1. A non-volatile memory device comprising:

a floating gate formed on a substrate with a gate insulation layer interposed therebetween;

a tunnel insulation layer formed on the floating gate;

a select gate electrode inducing charge through the gate insulation layer;

a control gate electrode inducing charge tunneling through the tunnel insulation layer and wherein at least a portion of the select gate electrode and at least a portion of the control gate electrode are formed directly on the gate insulation layer, wherein the select gate electrode comprising;

a top select gate electrode formed over the floating gate;

and a sidewall select gate electrode formed on a sidewall of the floating gate and the gate insulation layer opposite to the control gate electrode; and

a spacer insulation pattern interposed between the top select gate electrode and the sidewall select gate electrode and between the top select gate electrode and the control gate electrode.

2. The non-volatile memory device of claim 1, wherein the select gate electrode is insulated from the floating gate by a dielectric layer, and the control gate electrode is insulated from the floating gate by the tunnel insulation layer.

3. The non-volatile memory device of claim 2, wherein a capacitance between the select gate electrode and the floating gate is higher than a capacitance between the control gate electrode and the floating gate.

4. The non-volatile memory device of claim 3, wherein the dielectric layer includes a material having a higher dielectric constant than the tunnel insulation layer.

5. The non-volatile memory device of claim 1, wherein the floating gate has a tip formed toward the control gate electrode.

6. The non-volatile memory device of claim 5, wherein the charge tunneling through the tunnel insulation layer occurs around the tip of the floating gate.

7. The non-volatile memory device of claim 1, further comprising:

source region and a drain region defining a channel region in a semiconductor substrate,

wherein the floating gate, the select gate electrode, and the control gate electrode are formed on the channel region with the gate insulation layer interposed therebetween.

8. The non-volatile memory device of claim 7, wherein hot carriers generated at the channel region by the induction of the select gate electrode are injected through the gate insulation layer.

9. A non-volatile memory device according to claim 1, further comprising:

source region and a drain region defining a channel region in the substrate; and

an intergate dielectric interposed between the select gate electrode and the floating gate, and wherein the gate insulation layer is formed on the channel region;

the select gate electrode is formed on the gate insulation layer and the floating gate,

the control gate electrode is formed on a sidewall of the floating gate and the gate insulation layer to be opposite to the select gate electrode, and

the tunnel insulation layer is interposed between the control gate electrode and the floating gate.

10. The non-volatile memory device of claim 9, wherein an area of the intergate dielectric between the select gate electrode and the floating gate is larger than an area of the tunnel insulation layer between the control gate electrode and the floating gate.

11. The non-volatile memory device of claim 9, wherein the sidewall select gate electrode and the control gate electrode are symmetrical with each other.

12. The non-volatile memory device of claim 9, wherein the intergate dielectric between the top select gate electrode and the floating gate includes a material having a higher dielectric constant than the tunnel insulation layer.

13. The non-volatile memory device of claim 12, wherein an interlayer dielectric between the sidewall select gate electrode and the floating gate is made of the same material as the tunnel insulation layer.