Multiplier array processing system with enhanced utilization at lower precision

• US 7,509,366 B2
• Filed: 04/18/2003
• Issued: 03/24/2009
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Hansen, Craig C.
• Primary Examiner(s): Malzahn; David H
• Application Number:
  US10/418,113
• Publication Number:
  US 20040015533A1
• Time in Patent Office: 2,167 Days
• Field of Search: 708/620, 708/420, 708/501, 708/523, 708/603, 712/221
• US Class Current: 708/501
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/238 Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams hybrid fiber coaxial [HFC] networks for downstream channel allocation for video distribution H04L12/2801; flow control in packet networks H04L47/10; real-time communication protocols in data switching networks H04L65/00; scheduling or organising the servicing of application requests H04L67/60
• CPC Class Codes: H04N 21/23805 Controlling the feeding rate to the network, e.g. by controlling the video pump
• CPC Class Codes: H04N 21/4347 : Demultiplexing of several video streams
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.

Claims

1. A method for performing a group-multiply-add instruction in a programmable processor, the method comprising:

partitioning a first register, a second register, and a third register into a plurality of floating-point operands;

multiplying, in parallel, the plurality of floating-point operands from the first register by the plurality of floating-point operands from the second register and adding the plurality of floating-point operands from the third register, producing a plurality of floating-point numbers; and

providing the plurality of floating-point numbers to a plurality of partitioned fields of a result.

2. The method of claim 1 wherein the floating-point operands of the first register, the second register, the third register, and of the result are each capable of being represented by equal defined bit widths.

3. The method of claim 1 wherein the floating-point operands of the first register, the second register, and of the result are each capable of being represented by equal defined bit widths.

4. The method of claim 1 wherein the floating-point operands of the third register and of the result are each capable of being represented by equal defined bit widths.

5. The method of claim 1 wherein each of the first, second, and third registers are partitionable into four fields to hold four floating-point operands in parallel.

6. The method of claim 1 wherein the first, second, and third registers are 128 bit registers.

7. The method of claim 1 wherein the result is returned to a result register.

8. The method of claim 7 wherein the result register is a different register than either the first, second, or third registers.

9. A programmable processor for performing a group-multiply-add instruction, the processor comprising:

first, second, and third registers partitioned into a plurality of floating-point operands; and

a multiplier and adder array, configured to multiply, in parallel, the plurality of floating-point operands from the first register by the plurality of floating-point operands from the second register and add the plurality of floating-point operands from the third register to produce a plurality of floating-point numbers; and

to provide the plurality of floating-point numbers to a plurality of partitioned fields of a result.

10. The processor of claim 9 wherein the floating-point operands of the first register, the second register, the third register, and of the result are each capable of being represented by equal defined bit widths.

11. The processor of claim 9 wherein the floating-point operands of the first register, the second register, and of the result are each capable of being represented by equal defined bit widths.

12. The processor of claim 9 wherein the floating-point operands of the third register and of the result are each capable of being represented by equal defined bit widths.

13. The processor of claim 9 wherein each of the first, second, and third registers are partitionable into four fields to hold four floating-point operands in parallel.

14. The processor of claim 9 wherein the first, second, and third registers are 128 bit registers.

15. The processor of claim 9 further comprising:

fourth, fifth and sixth registers partitioned to into a plurality of fixed-point operands,

wherein the multiplier and adder array is further configurable to multiply, in parallel, the plurality of fixed-point operands from the fourth register by a plurality of fixed-point operands from the fifth register and add the plurality of fixed-point operands from the sixth register to produce the plurality of fixed-point numbers; and

to provide the plurality of fixed-point numbers to a plurality of partitioned fields of a result.

16. The processor of claim 9 wherein the multiplier and adder array is further configured for performing a group-multiply instruction for a plurality of floating-point operands.

17. The processor of claim 9 further comprising:

fourth and fifth registers partitioned to into a plurality of fixed-point operands,

wherein the multiplier and adder array is further configurable to multiply, in parallel, the plurality of fixed-point operands from the fourth register by a plurality of fixed-point operands from the fifth register to produce the plurality of fixed-point numbers; and

to provide the plurality of fixed-point numbers to the plurality of partitioned fields of a result.

18. The processor of claim 9 wherein the result is returned to a result register.

19. The processor of claim 18 wherein the result register is a different register than either the first, second, or third registers.