Software-hardware partitioning of a scheduled medium-access protocol

• US 7,525,971 B2
• Filed: 03/16/2005
• Issued: 04/28/2009
• Est. Priority Date: 03/16/2005
• Status: Active Grant

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Alcatel-Lucent USA, Inc. (Nokia Corporation)
• Inventors: Hadzic, Ilija, Suvakovic, Dusan, Carroll, Martin D.
• Primary Examiner(s): HAN, CLEMENCE S
• Application Number:
  US11/081,932
• Publication Number:
  US 20060209825A1
• Time in Patent Office: 1,504 Days
• Field of Search: None
• US Class Current: 370/395.4
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS

Abstract

A processing device, configured to implement at least a portion of a scheduled medium-access protocol (SMAP) in a communication system, comprises a processor, a memory coupled to the processor, and one or more additional hardware modules. The functionality of the portion of the SMAP implemented in the processing device is partitioned between software, stored in the memory and executable by the processor, and hardware comprising the one or more additional hardware modules. In an illustrative embodiment, the processing device comprises a head-end device of a passive optical network, and the functionality comprises at least a scheduler and a grant generator, with the scheduler being implemented in the software and the grant generator being implemented in the hardware.

Claims

1. A processing device for implementing at least a portion of a scheduled medium-access protocol in a communication system, the processing device comprising:

a processor;

a memory coupled to the processor; and

one or more additional hardware modules;

wherein functionality of the portion of the scheduled medium-access protocol implemented in the processing device is partitioned between software stored in the memory and executable by the processor and hardware comprising the one or more additional hardware modules;

the functionality comprising at least a scheduler and a grant generator;

wherein the scheduler is implemented in the software and the grant generator is implemented in the hardware;

wherein the scheduler generates updated schedules at a rate which is independent of a rate at which the grant generator generates upstream channel access grants for subscriber devices of the system.

2. The processing device of claim 1 wherein the processing device comprises a head-end device coupled between an access network of the communication system and an external network of the communication system.

3. The processing device of claim 2 wherein the access network is coupled via subscriber devices of the system to respective subscriber networks of the system.

4. The processing device of claim 2 wherein the scheduler determines a schedule for permitting subscriber devices of the system to access an upstream channel of the system from the access network to the external network via the head-end device.

5. The processing device of claim 2 wherein the functionality further comprises a discovery module operative to allow the head-end device to discover when subscriber devices of the system join or leave the access network.

6. The processing device of claim 2 wherein the one or more additional hardware modules further comprise external network transmit and receive modules, and access network transmit and receive modules.

7. The processing device of claim 1 wherein the functionality further comprises a report processor operative to determine current bandwidth needs for subscriber devices of the system, the report processor being implemented in the hardware.

8. The processing device of claim 1 wherein the communication system comprises a passive optical network and the scheduled medium-access protocol comprises a passive optical network protocol.

9. The processing device of claim 1 wherein the one or more additional hardware modules comprise at least one of a network processor, a programmable logic device, and an application-specific integrated circuit.

10. The processing device of claim 1 wherein the memory stores at least one report table data structure, the report table data structure defining a current state of subscriber devices known to the system.

11. The processing device of claim 1 wherein the memory stores at least one schedule data structure, the schedule data structure defining a schedule computed in the software by the scheduler.

12. The processing device of claim 11 wherein a given entry in the schedule data structure comprises at least one of the following:

(i) start time and length of up to a designated number of grants, (ii) a flags bitmask, and (iii) a pointer to a next entry in the schedule.

13. The processing device of claim 1 wherein the grant generator issues a set of grants each grant period in accordance with a basic schedule comprising a linked list of grants which enforces grant period and minimum guaranteed bandwidth constraints for subscriber devices of the system.

14. The processing device of claim 1 wherein the processing device is implemented as at least one integrated circuit.

15. A processing device for implementing at least a portion of a scheduled medium-access protocol in a communication system, the processing device comprising:

a processor;

a memory coupled to the processor; and

one or more additional hardware modules;

wherein functionality of the portion of the scheduled medium-access protocol implemented in the processing device is partitioned between software stored in the memory and executable by the processor and hardware comprising the one or more additional hardware modules;

the functionality comprising at least a scheduler and a grant generator;

wherein the scheduler is implemented in the software and the grant generator is implemented in the hardware; and

wherein a plurality of schedule data structures are stored in the memory, at least one of the schedule data structures defining a schedule computed in the software by the scheduler, the grant generator utilizing a first one of the schedule data structures to generate upstream channel access grants for subscriber devices of the system, the scheduler using a second one of the schedule data structures to update the schedule.

16. The processing device of claim 15 wherein the scheduler, after updating the schedule using the second schedule data structure, is operative to direct the grant generator to switch from utilization of the first schedule data structure to utilization of the second schedule data structure in generating the upstream channel access grants.

17. A processing device for implementing at least a portion of a scheduled medium-access protocol in a communication system, the processing device comprising:

a processor;

a memory coupled to the processor; and

one or more additional hardware modules;

wherein functionality of the portion of the scheduled medium-access protocol implemented in the processing device is partitioned between software stored in the memory and executable by the processor and hardware comprising the one or more additional hardware modules;

the functionality comprising at least a scheduler and a grant generator;

wherein the scheduler is implemented in the software and the grant generator is implemented in the hardware; and

wherein the grant generator issues grants in accordance with an enhanced schedule comprising an ordered list of basic schedules, each of which defines grants for a corresponding set of time units in an upstream channel of the system.

18. The processing device of claim 17 wherein every π

_G time units the grant generator issues the grants for a given basic schedule S_i and then advances a pointer to a next basic schedule in the ordered list.

19. A processing device for implementing at least a portion of a scheduled medium-access protocol in a communication system, the processing device comprising:

a processor;

a memory coupled to the processor; and

one or more additional hardware modules;

wherein functionality of the portion of the scheduled medium-access protocol implemented in the processing device is partitioned between software stored in the memory and executable by the processor and hardware comprising the one or more additional hardware modules;

the functionality comprising at least a scheduler, a discovery element and a grant processor;

wherein the discovery element is implemented in the software and the grant processor is implemented in the hardware;

wherein the scheduler generates updated schedules at a rate which is independent of a rate at which the grant generator generates upstream channel access grants for subscriber devices of the system.

20. A method of implementing at least a portion of a scheduled medium-access protocol in a processing device of a communication system, the processing device comprising a processor, a memory coupled to the processor, and one or more additional hardware modules, the method comprising:

partitioning functionality of the portion of the scheduled medium-access protocol implemented in the processing device between software stored in the memory and executable by the processor and hardware comprising the one or more additional hardware modules;

the functionality comprising at least a scheduler and a grant generator;

wherein the scheduler is implemented in the software and the grant generator is implemented in the hardware;

wherein the scheduler generates updated schedules at a rate which is independent of a rate at which the grant generator generates upstream channel access grants for subscriber devices of the system.

21. The method of claim 20 wherein the functionality further comprises a report processor operative to determine current bandwidth needs for subscriber devices of the system, the report processor being implemented in the hardware.

22. The method of claim 20 wherein a plurality of schedule data structures are stored in the memory, at least one of the schedule data structures defining a given schedule computed in the software by the scheduler, the grant generator utilizing a first one of the schedule data structures to generate upstream channel access grants for subscriber devices of the system, the scheduler using a second one of the schedule data structures to update the given schedule.